Abstract: A sequential asynchronous system and a method for operating the same. The method includes operating a first asynchronous finite state machine at a first clock rate and operating a second asynchronous finite state machine at a second clock rate. The method also includes generating, with fork logic, a fork request based on a first state of the first asynchronous finite state machine and receiving, with join logic, the fork request from the fork logic. The method further includes receiving, with the join logic, a communication request from the second asynchronous finite state machine based on a second state of the second asynchronous finite state machine and initiating, with the join logic, a state transition of the second asynchronous finite state machine. The method also includes providing, with the join logic, a join acknowledgement to the fork logic upon completion of the state transition.

Abstract: A sequential asynchronous system and a method for operating the same. The method includes operating a first asynchronous finite state machine at a first clock rate and operating a second asynchronous finite state machine at a second clock rate. The method also includes generating, with fork logic, a fork request based on a first state of the first asynchronous finite state machine and receiving, with join logic, the fork request from the fork logic. The method further includes receiving, with the join logic, a communication request from the second asynchronous finite state machine based on a second state of the second asynchronous finite state machine and initiating, with the join logic, a state transition of the second asynchronous finite state machine. The method also includes providing, with the join logic, a join acknowledgement to the fork logic upon completion of the state transition.

Abstract: Technology is described for an asynchronous wrapper circuit for a clock gating cell (CGC). In one example, the asynchronous wrapper cell for CGC includes circuitry configured to (1) sample a data channel via sampling circuitry for a communication start signal to enable the CGC to start a gated clock for a data message on the data channel, and (2) reset an enable of the CGC to an idle mode via idle mode control circuitry after the data message has been clocked via the CGC through function cell circuitry. The idle mode control circuitry generates an output for the sampling circuitry from the function cell. Various other computing circuitries are also disclosed.

Abstract: Technology is described for an asynchronous wrapper circuit for a clock gating cell (CGC). In one example, the asynchronous wrapper cell for CGC includes circuitry configured to (1) sample a data channel via sampling circuitry for a communication start signal to enable the CGC to start a gated clock for a data message on the data channel, and (2) reset an enable of the CGC to an idle mode via idle mode control circuitry after the data message has been clocked via the CGC through function cell circuitry. The idle mode control circuitry generates an output for the sampling circuitry from the function cell. Various other computing circuitries are also disclosed.