Patents by Inventor Dipanjan Sengupta

Dipanjan Sengupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11853766
    Abstract: An example system includes memory; a central processing unit (CPU) to execute first operations; in-memory execution circuitry in the memory; and detector software to cause offloading of second operations to the in-memory execution circuitry, the in-memory execution circuitry to execute the second operations in parallel with the CPU executing the first operations.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Vy Vo, Dipanjan Sengupta, Mariano Tepper, Javier Sebastian Turek
  • Patent number: 11829376
    Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Mariano Tepper, Dipanjan Sengupta, Jawad Khan, Sourabh Dongaonkar, Chetan Chauhan, Richard Coulson, Theodore Willke
  • Publication number: 20230305709
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.
    Type: Application
    Filed: September 15, 2020
    Publication date: September 28, 2023
    Inventors: Dipanjan Sengupta, Mariano Tepper, Sourabh Dongaonkar, Chetan Chauhan, Jawad Khan, Theodore Willke, Richard Coulson
  • Patent number: 11674163
    Abstract: The present invention relates to processes and intermediates useful in the preparation of (R)-2-(7-(4-cyclopentyl-3-(trifluoromethyl)benzyloxy)-1,2,3,4-tetrahydrocyclopenta[b]indol-3-yl)acetic acid of Formula (Ia) and salts thereof, an S1P1 receptor modulator that is useful in the treatment of S1P1 receptor-associated disorders, for example, diseases and disorders mediated by lymphocytes, transplant rejection, autoimmune diseases and disorders, inflammatory diseases and disorders (e.g., acute and chronic inflammatory conditions), cancer, and conditions characterized by an underlying defect in vascular integrity or that are associated with angiogenesis such as may be pathologic (e.g., as may occur in inflammation, tumor development and atherosclerosis).
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: June 13, 2023
    Assignee: Arena Pharmaceuticals, Inc.
    Inventors: Antonio Garrido Montalban, Daniel J. Buzard, John A. DeMattei, Tawfik Gharbaoui, Stephen R. Johannsen, Ashwin M. Krishnan, Young Mi Kuhlman, You-An Ma, Michael John Martinelli, Suzanne Michiko Sato, Dipanjan Sengupta
  • Patent number: 11604834
    Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Mariano Tepper, Dipanjan Sengupta, Sourabh Dongaonkar, Chetan Chauhan, Jawad Khan, Theodore Willke, Richard Coulson, Rajesh Sundaram
  • Patent number: 11574172
    Abstract: Technologies for efficiently performing memory augmented neural network (MANN) update operations includes a device with circuitry configured to obtain a key usable to search a memory associated with a memory augmented neural network for one or more data sets. The circuitry is also configured to perform a stochastic associative search to identify a group of data sets within the memory that satisfy the key and write to the identified group of data sets concurrently to update the memory augmented neural network.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Dipanjan Sengupta, Jawad B. Khan, Theodore Willke, Richard Coulson
  • Patent number: 11507773
    Abstract: Systems, apparatuses and methods may store a plurality of classes that represent a plurality of clusters in a cache. Each of the classes represents a group of the plurality of clusters and the plurality of clusters is in a first data format. The systems, apparatuses and methods further modify input data from a second data format to the first data format and conduct a similarity search based on the input data in the first data format to assign the input data to at least one class of the classes.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Mariano Tepper, Dipanjan Sengupta, Theodore Willke, Javier Sebastian Turek
  • Patent number: 11500887
    Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Sourabh Dongaonkar, Jawad B. Khan, Chetan Chauhan, Dipanjan Sengupta, Mariano Tepper, Theodore Willke, Richard L. Coulson
  • Publication number: 20220357951
    Abstract: An example system includes memory; a central processing unit (CPU) to execute first operations; in-memory execution circuitry in the memory; and detector software to cause offloading of second operations to the in-memory execution circuitry, the in-memory execution circuitry to execute the second operations in parallel with the CPU executing the first operations.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Vy Vo, Dipanjan Sengupta, Mariano Tepper, Javier Sebastian Turek
  • Publication number: 20220259627
    Abstract: The present invention relates to processes and intermediates useful in the preparation of of (R)-2-(7-(4-cyclopentyl-3-(trifluoromethyl)benzyloxy)-1,2,3,4-tetrahydrocyclopenta[b]indol-3-yl)acetic acid of Formula (Ia) and salts thereof, an S1P1 receptor modulator that is useful in the treatment of S1P1 receptor-associated disorders, for example, diseases and disorders mediated by lymphocytes, transplant rejection, autoimmune diseases and disorders, inflammatory diseases and disorders (e.g., acute and chronic inflammatory conditions), cancer, and conditions characterized by an underlying defect in vascular integrity or that are associated with angiogenesis such as may be pathologic (e.g., as may occur in inflammation, tumor development and atherosclerosis).
    Type: Application
    Filed: September 14, 2021
    Publication date: August 18, 2022
    Inventors: Antonio Garrido Montalban, Daniel J. Buzard, John A. DeMattei, Tawfik Gharbaoui, Stephen R. Johannsen, Ashwin M. Krishnan, Young Mi Kuhlman, You-An Ma, Michael John Martinelli, Suzanne Michiko Sato, Dipanjan Sengupta
  • Patent number: 11403102
    Abstract: Systems, apparatuses and methods may provide for technology that recognizes, via a neural network, a pattern of memory access and compute instructions based on an input set of machine instructions, determines, via a neural network, a sequence of instructions to be offloaded for execution by the secondary computing device based on the recognized pattern of memory access and compute instructions, and translates the sequence of instructions to be offloaded from instructions executable by a central processing unit (CPU) into instructions executable by the secondary computing device.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Vy Vo, Dipanjan Sengupta, Mariano Tepper, Javier Sebastian Turek
  • Patent number: 11392494
    Abstract: Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Jawad Khan, Chetan Chauhan, Rajesh Sundaram, Sourabh Dongaonkar, Sandeep Guliani, Dipanjan Sengupta, Mariano Tepper
  • Patent number: 11327881
    Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Chetan Chauhan, Sourabh Dongaonkar, Rajesh Sundaram, Jawad Khan, Sandeep Guliani, Dipanjan Sengupta, Mariano Tepper
  • Patent number: 11149292
    Abstract: The present invention relates to processes and intermediates useful in the preparation of (R)-2-(7-(4-cyclopentyl-3-(trifluoromethyl)benzyloxy)-1,2,3,4-tetrahydrocyclopenta[b]indol-3-yl)acetic acid of Formula (Ia) and salts thereof, an S1P1 receptor modulator that is useful in the treatment of S1P1 receptor-associated disorders, for example, diseases and disorders mediated by lymphocytes, transplant rejection, autoimmune diseases and disorders, inflammatory diseases and disorders (e.g., acute and chronic inflammatory conditions), cancer, and conditions characterized by an underlying defect in vascular integrity or that are associated with angiogenesis such as may be pathologic (e.g., as may occur in inflammation, tumor development and atherosclerosis).
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 19, 2021
    Assignee: Arena Pharmaceuticals, Inc.
    Inventors: Antonio Garrido Montalban, Daniel J. Buzard, John A. DeMattei, Tawfik Gharbaoui, Stephen R. Johannsen, Ashwin M. Krishnan, Young Mi Kuhlman, You-An Ma, Michael John Martinelli, Suzanne Michiko Sato, Dipanjan Sengupta
  • Publication number: 20210318805
    Abstract: Binary sparse encoding of data can be used to reduce an amount of data read from the stochastic associative memory while processing a query. Read performance of the stochastic associated memory is optimized to enhance the query throughput by modifying access patterns to reduce the time to read the stochastic associated memory. Read performance of the stochastic associative memory can be further improved through the use of cluster aware sharding and replication for parallelized similarity search. Clusters are partitioned across multiple Dual In-line Memory Modules (DIMMs), each DIMM including stochastic associative memory, to achieve maximum latency advantage.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Sourabh DONGAONKAR, Jawad B. KHAN, Chetan CHAUHAN, Dipanjan SENGUPTA, Mariano TEPPER, Theodore WILLKE
  • Publication number: 20210224267
    Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 22, 2021
    Inventors: Sourabh DONGAONKAR, Jawad B. KHAN, Chetan CHAUHAN, Dipanjan SENGUPTA, Mariano TEPPER, Theodore WILLKE, Richard L. COULSON
  • Publication number: 20200327365
    Abstract: Systems, apparatuses and methods may store a plurality of classes that represent a plurality of clusters in a cache. Each of the classes represents a group of the plurality of clusters and the plurality of clusters is in a first data format. The systems, apparatuses and methods further modify input data from a second data format to the first data format and conduct a similarity search based on the input data in the first data format to assign the input data to at least one class of the classes.
    Type: Application
    Filed: June 27, 2020
    Publication date: October 15, 2020
    Inventors: Mariano Tepper, Dipanjan Sengupta, Theodore Willke, Javier Sebastian Turek
  • Publication number: 20200327118
    Abstract: Systems, apparatuses and methods may provide for technology that identifies a query code, translates the query code into a query graph, generates a candidate vector based on a candidate graph, wherein the candidate graph is associated with a candidate code, generates a query vector based on the query graph, and determines a similarity measurement between the query vector and the candidate vector.
    Type: Application
    Filed: June 27, 2020
    Publication date: October 15, 2020
    Inventors: Nesreen K. Ahmed, Dipanjan Sengupta, Todd Anderson, Theodore Willke
  • Publication number: 20200326949
    Abstract: Systems, apparatuses and methods may provide for technology that recognizes, via a neural network, a pattern of memory access and compute instructions based on an input set of machine instructions, determines, via a neural network, a sequence of instructions to be offloaded for execution by the secondary computing device based on the recognized pattern of memory access and compute instructions, and translates the sequence of instructions to be offloaded from instructions executable by a central processing unit (CPU) into instructions executable by the secondary computing device.
    Type: Application
    Filed: June 27, 2020
    Publication date: October 15, 2020
    Inventors: Vy Vo, Dipanjan Sengupta, Mariano Tepper, Javier Sebastian Turek
  • Publication number: 20200301828
    Abstract: Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Jawad Khan, Chetan Chauhan, Rajesh Sundaram, Sourabh Dongaonkar, Sandeep Guliani, Dipanjan Sengupta, Mariano Tepper