Abstract: Epitaxial films are grown by alternately exposed to precursor dosing regions, inert gas plasma regions, hydrogen-containing plasma regions, chlorine-containing plasma and metrology regions, or regions where an atomic hydrogen source is located. Alternately, laser irradiation techniques may be substituted for the plasma energy in some of the processing regions. The film growth process can be implemented at substrate temperatures between about 25 C and about 600 C, together with optional exposures to laser irradiation to cause the surface of the film to melt or to experience a near-melt condition.

Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract: CMOS imaging sensors having fluorine-passivated structures to reduce dark current are disclosed together with methods of making thereof. The CIS comprises an array of pixels on a substrate, each pixel comprising a pinned photodiode, an isolation trench adjacent to the pinned photodiode, and a plurality of transistors. Methods of preparing a CIS comprise providing a source of fluorine (F) atoms, and annealing in the presence of the source of F atoms. After the annealing, at least one silicon-containing surface or region in the CIS comprises Si—F bonds and is fluorine passivated.

Abstract: Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-? dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts.

Abstract: A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant.

Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (?fG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

Abstract: Combinatorial processing of a substrate comprising site-isolated sputter deposition and site-isolated plasma processing can be performed in a same process chamber. The process chamber, configured to perform sputter deposition and plasma processing, comprises a grounded shield having at least an aperture disposed above the substrate to form a small, dark space gap to reduce or eliminate any plasma formation within the gap. The plasma processing may include plasma etching or plasma surface treatment.

Abstract: Systems and methods for improving the performance of one way mirror applications are disclosed. Methods consistent with the present disclosure include introducing a glass substrate into a processing chamber. The processing chamber comprises a sputter target assembly disposed over the substrate. Next, depositing metal silicide material within a plurality of site-isolated regions on the substrate to form a metal silicide coating within each region. Notably, each metal silicide coating has a thickness between 0.001 and 0.5 microns. Finally, evaluating results of the metal silicide coating formed within the plurality of site-isolated regions.

Abstract: Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging.

Abstract: A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

Abstract: Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 C above the operating temperature. The memory chip can include embedded heaters in the chip package, allowing for heating the memory cells before the programming operations.

Abstract: Resistive random access memory (ReRAM) cells can include an embedded metal nanoparticle switching layer and electrodes. The metal nanoparticles can be formed using a micelle solution. The generation of the nanoparticles can be controlled in multiple dimensions to achieve desirable performance characteristics, such as low power consumption as well as low and consistent switching currents.

Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

Abstract: Epitaxial films are grown by alternately exposed to precursor dosing regions, inert gas plasma regions, hydrogen-containing plasma regions, chlorine-containing plasma and metrology regions, or regions where an atomic hydrogen source is located. Alternately, laser irradiation techniques may be substituted for the plasma energy in some of the processing regions. The film growth process can be implemented at substrate temperatures between about 25 C and about 600 C, together with optional exposures to laser irradiation to cause the surface of the film to melt or to experience a near-melt condition.

Abstract: Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm.