Patents by Inventor Diptendu Ghosh
Diptendu Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12047042Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.Type: GrantFiled: November 30, 2021Date of Patent: July 23, 2024Assignee: Silicon Laboratories Inc.Inventors: Diptendu Ghosh, Mustafa H. Koroglu, Dayasagar Gaade, Francesco Barale
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Publication number: 20230170855Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Diptendu Ghosh, Mustafa H. Koroglu, Dayasagar Gaade, Francesco Barale
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Patent number: 9900022Abstract: DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be ±LC notch filters (with ±Ln notch inductors), and the peaking filter can be ±Ls peaking inductors coupled in series to the ±LC notch filters. The ±Ln notch inductors, ±Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ± signal paths are implemented with differential DAC designs including passive reconstruction filters.Type: GrantFiled: January 17, 2017Date of Patent: February 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Diptendu Ghosh, Petteri Matti Litmanen, Siraj Akhtar
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Publication number: 20170207795Abstract: A DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter (low pass filter with peaking in the signal passband). The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency contents at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with at least one notch inductor Ln and at least one notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be configured with ±LC notch filters (with ±Ln notch inductors), and the peaking filter can be ±Ls peaking inductors coupled in series to the ±LC notch filters. The ±Ln notch inductors, ±Ls peaking inductors can be mutually wound as single inductors.Type: ApplicationFiled: January 17, 2017Publication date: July 20, 2017Inventors: Diptendu Ghosh, Petteri Matti Litmanen, Siraj Akhtar
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Publication number: 20170207774Abstract: A latch circuit includes first and second inverters, each with latching (inner) and clocking (outer) PMOS/NMOS transistor pairs in a series/stack configuration. A first inverter includes a D_latching PMOS/NMOS transistor pair, drain-connected at a D node. A first /clock PMOS transistor is coupled between a high rail and a source terminal of the D_latching PMOS transistor, and a first clock NMOS transistor is coupled between a low rail and the source terminal of the D_latching NMOS transistor. A second inverter includes a Dbar_latching PMOS/NMOS transistor pair, drain-connected at a Dbar node. A second /clock PMOS transistor is coupled between the high rail and the source terminal of the Dbar_latching PMOS transistor, and a second clock NMOS transistor is coupled between the low rail and the Dbar_latching NMOS transistor. A cross-coupling switch circuit connected between the D node and the Dbar node.Type: ApplicationFiled: January 17, 2017Publication date: July 20, 2017Inventors: Diptendu Ghosh, Petteri Matti Litmanen, Siraj Akhtar
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Patent number: 8421510Abstract: Within hard disk drives (HDDs), for example, a preamplifier or preamp is generally used to perform read and write operations with a magnetic head. Typically, for write operations, the preamplifier generates a current waveform that uses a DC current to polarize magnetic elements within the disk and overshoot components to compensate for frequency dependent attenuation in the interconnect between the head and preamp. Conventional pulse-shaping circuitry used for this application uses high voltage to accomplish this task. Here, however, pulse-shaping circuitry is provided which can generate a similar waveform using lower voltage (i.e., about 5V) for this application and others.Type: GrantFiled: May 4, 2011Date of Patent: April 16, 2013Assignee: Texas Instruments IncorporatedInventors: Diptendu Ghosh, Rajarshi Mukhopadhyay, Reza Sharifi
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Publication number: 20110304373Abstract: Within hard disk drives (HDDs), for example, a preamplifier or preamp is generally used to perform read and write operations with a magnetic head. Typically, for write operations, the preamplifier generates a current waveform that uses a DC current to polarize magnetic elements within the disk and overshoot components to compensate for frequency dependent attenuation in the interconnect between the head and preamp. Conventional pulse-shaping circuitry used for this application uses high voltage to accomplish this task. Here, however, pulse-shaping circuitry is provided which can generate a similar waveform using lower voltage (i.e., about 5V) for this application and others.Type: ApplicationFiled: May 4, 2011Publication date: December 15, 2011Applicant: Texas Instruments IncorporatedInventors: Diptendu Ghosh, Rajarshi Mukhopadhyay, Reza Sharifi
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Patent number: 7961056Abstract: Embodiments of the present invention include a low phase noise oscillator circuit using a current-reuse technique to reduce power consumption and improve phase noise, where the oscillator circuit comprises a first VCO coupled to a second VCO, and the outputs of the first and second VCOs are coupled with passive elements, such as capacitors. The overall power consumption of both the first and second VCOs is about the same as a single VCO. Furthermore, the phase noise is lowered by around 3 dB. Thus, the phase noise performance is improved without increasing the power consumption of the oscillator circuit.Type: GrantFiled: September 10, 2009Date of Patent: June 14, 2011Assignee: Intel CorporationInventors: Stewart S. Taylor, Diptendu Ghosh
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Publication number: 20110057732Abstract: Embodiments of the present invention include a low phase noise oscillator circuit using a current-reuse technique to reduce power consumption and improve phase noise, where the oscillator circuit comprises a first VCO coupled to a second VCO, and the outputs of the first and second VCOs are coupled with passive elements, such as capacitors. The overall power consumption of both the first and second VCOs is about the same as a single VCO. Furthermore, the phase noise is lowered by around 3 dB.Type: ApplicationFiled: September 10, 2009Publication date: March 10, 2011Inventors: Stewart S. Taylor, Diptendu Ghosh