Patents by Inventor Dipti Ranjan Pal
Dipti Ranjan Pal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11880454Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.Type: GrantFiled: May 14, 2020Date of Patent: January 23, 2024Assignee: QUALCOMM IncorporatedInventors: Bharat Kumar Rangarajan, Dipti Ranjan Pal, Keith Alan Bowman, Srinivas Turaga, Ateesh Deepankar De, Shih-Hsin Jason Hu, Chandan Agarwalla
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Patent number: 11855645Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.Type: GrantFiled: September 25, 2021Date of Patent: December 26, 2023Assignee: QUALCOMM INCORPORATEDInventors: Keith Alan Bowman, Daniel Yingling, Dipti Ranjan Pal
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Publication number: 20230096760Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.Type: ApplicationFiled: September 25, 2021Publication date: March 30, 2023Inventors: Keith Alan BOWMAN, Daniel YINGLING, Dipti Ranjan PAL
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Publication number: 20220365580Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.Type: ApplicationFiled: May 17, 2021Publication date: November 17, 2022Inventors: VIJAYAKUMAR ASHOK DIBBAD, Bharat Kumar RANGARAJAN, Dipti Ranjan PAL, Keith Alan BOWMAN, Matthew SEVERSON, Gordon LEE
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Patent number: 11493980Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.Type: GrantFiled: May 17, 2021Date of Patent: November 8, 2022Assignee: QUALCOMM IncorporatedInventors: Vijayakumar Ashok Dibbad, Bharat Kumar Rangarajan, Dipti Ranjan Pal, Keith Alan Bowman, Matthew Severson, Gordon Lee
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Patent number: 11493970Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.Type: GrantFiled: October 30, 2020Date of Patent: November 8, 2022Assignee: QUALCOMM IncorporatedInventors: Christopher Kong Yee Chun, Chandan Agarwalla, Dipti Ranjan Pal, Kumar Kanti Ghosh, Matthew Severson, Nilanjan Banerjee, Joshua Stubbs
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Patent number: 11424736Abstract: Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices, and combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal.Type: GrantFiled: September 25, 2021Date of Patent: August 23, 2022Assignee: QUALCOMM INCORPORATEDInventors: Keith Alan Bowman, Daniel Yingling, Dipti Ranjan Pal
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Patent number: 11398812Abstract: A method of measuring a clock signal includes launching an edge of a timing signal on a first edge of the clock signal, outputting an edge of a capture signal on a second edge of the clock signal, receiving the edge of the timing signal and the edge of the capture signal at a time-to-digital converter (TDC), and measuring a time delay using the TDC, wherein the time delay is between a time the edge of the timing signal is received at the TDC and a time the edge of the capture signal is received at the TDC.Type: GrantFiled: September 25, 2021Date of Patent: July 26, 2022Assignee: QUALCOMM INCORPORATEDInventors: Keith Alan Bowman, Daniel Yingling, Dipti Ranjan Pal
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Publication number: 20220137687Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Inventors: Christopher Kong Yee CHUN, Chandan AGARWALLA, Dipti Ranjan PAL, Kumar Kanti GHOSH, Matthew SEVERSON, Nilanjan BANERJEE, Joshua STUBBS
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Patent number: 11249530Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.Type: GrantFiled: November 25, 2020Date of Patent: February 15, 2022Assignee: QUALCOMM INCORPORATEDInventors: Dipti Ranjan Pal, Harshat Pant, Abinash Roy, Shih-Hsin Jason Hu, Keith Alan Bowman
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Publication number: 20210357502Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.Type: ApplicationFiled: May 14, 2020Publication date: November 18, 2021Inventors: Bharat Kumar RANGARAJAN, Dipti Ranjan PAL, Keith Alan BOWMAN, Srinivas TURAGA, Ateesh Deepankar DE, Shih-Hsin Jason HU, Chandan AGARWALLA
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Patent number: 10915157Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.Type: GrantFiled: February 14, 2019Date of Patent: February 9, 2021Assignee: QUALCOMM IncorporatedInventors: Dipti Ranjan Pal, Jeffrey Gemar, Abinash Roy
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Publication number: 20200264682Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.Type: ApplicationFiled: February 14, 2019Publication date: August 20, 2020Inventors: Dipti Ranjan PAL, Jeffrey GEMAR, Abinash ROY
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Publication number: 20190339757Abstract: Methods and apparatuses to power up multiple load circuits are presented. The apparatus includes a power delivery network, multiple load circuits configured to be powered via the power delivery network, and a wakeup control circuit configured to power up the multiple load circuits at a frequency based on a resonance frequency of the power delivery network. The method includes delivering power to the multiple load circuits by a power source via a power delivery network and powering up the multiple load circuits at a frequency, by a wakeup control circuit, based on a resonance frequency of the power delivery network.Type: ApplicationFiled: May 1, 2018Publication date: November 7, 2019Inventors: Abinash ROY, Dipti Ranjan PAL, Avinash GADDE
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Publication number: 20190324512Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Jason Edward PODAIMA, Christophe Denis Bernard AVOINNE, Manokanthan SOMASUNDARAM, Sina DENA, Paul Christopher John WIERCIENSKI, Bohuslav RYCHLIK, Steven John HALTER, Jaya Prakash SUBRAMANIAM GANASAN, Myil RAMKUMAR, Dipti Ranjan PAL
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Patent number: 10386904Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.Type: GrantFiled: March 31, 2016Date of Patent: August 20, 2019Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Christophe Denis Bernard Avoinne, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski, Bohuslav Rychlik, Steven John Halter, Jaya Prakash Subramaniam Ganasan, Myil Ramkumar, Dipti Ranjan Pal
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Patent number: 10250270Abstract: A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.Type: GrantFiled: May 23, 2018Date of Patent: April 2, 2019Assignee: QUALCOMM IncorporatedInventors: Kevin Bowles, Dipti Ranjan Pal
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Publication number: 20180278261Abstract: A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.Type: ApplicationFiled: May 23, 2018Publication date: September 27, 2018Inventors: Kevin Bowles, Dipti Ranjan Pal
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Patent number: 10014869Abstract: A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.Type: GrantFiled: March 8, 2017Date of Patent: July 3, 2018Assignee: QUALCOMM IncorporatedInventors: Kevin Bowles, Dipti Ranjan Pal
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Patent number: 9798376Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In one embodiment, a method for activating one or more processors comprises reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors. The method also comprises activating the one or more processors after the frequency of the clock signal is reduced, and increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated.Type: GrantFiled: August 3, 2015Date of Patent: October 24, 2017Assignee: QUALCOMM IncorporatedInventor: Dipti Ranjan Pal