Patents by Inventor Dipto THAKURTA

Dipto THAKURTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250261427
    Abstract: Integrated circuit structures having pre-spacer-deposition cut gates and associated defect test structures are described. For example, an integrated circuit structure includes a first and second fin or vertical arrangement of horizontal nanowires. First and second gate stacks are over the first and second fin or vertical arrangement of horizontal nanowires, respectively. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A dielectric structure has first and second portions forming a gate spacer along sidewalls of the first and second gate stacks, respectively, and a third portion completely filling the gap, the third portion continuous with the first and second portions. The integrated circuit structure also includes an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel with the first gate stack and the second gate stack.
    Type: Application
    Filed: February 14, 2024
    Publication date: August 14, 2025
    Inventors: Sairam SUBRAMANIAN, Xiao WEN, Dipto THAKURTA
  • Publication number: 20250246543
    Abstract: Voltage contrast (VC) image simulation capability and associated test structures are described. In an example, a circuit structure includes an inter-layer dielectric (ILD) layer. A plurality of unidirectional wires is in the ILD layer. In one specific example, the integrated circuit structure includes one or more additional wires in the ILD layer, the one or more additional wires along a direction different than a direction of the plurality of unidirectional wires, and the one or more additional wires are each continuous with a corresponding one of the plurality of unidirectional wires at a location between ends of the corresponding one of the plurality of unidirectional wires. In another specific example, one or more of the plurality of unidirectional wires have a line width transition therein.
    Type: Application
    Filed: June 27, 2024
    Publication date: July 31, 2025
    Inventors: Dipto THAKURTA, Gaurav RAJAVENDRA REDDY, Chaitanya Sai Chandra UMMADISETTY, Bhargav KORRAPATI
  • Publication number: 20250248127
    Abstract: Design of overlay-based front end defect quick turn test chip is described. In an example, an integrated circuit structure includes a device layer including a vertical stack of horizontal nanowires or a fin, a gate electrode over the vertical stack of horizontal nanowires or the fin, a conductive trench contact adjacent to the gate electrode, and a dielectric sidewall spacer between the gate electrode and the conductive trench contact. The integrated circuit structure also includes a metallization layer immediately above the device layer, the metallization layer including a first test pad and a second test pad.
    Type: Application
    Filed: June 27, 2024
    Publication date: July 31, 2025
    Inventors: Xiao WEN, Eduardo AKTINOL, Dipto THAKURTA, Sairam SUBRAMANIAN, Soumya BANERJEE, Saurabh BHANSALI
  • Publication number: 20240329114
    Abstract: An integrated circuit on a production die comprises a device under test (DUT) cell array formed in a fill region on the production die, the DUT cell array comprising a plurality of DUT transistor structures configured for voltage contrast (VC) detection of electrical opens on the production die. The DUT transistor structures comprise one or more vias that are not located on power lines or signal lines, such that the DUT transistor structures are not connected to each other or to the electrically functioning transistors. A guard ring buffer is formed at a transition between the active transistor region and the DUT cell array.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: Sairam Subramanian, Amit Paliwal, Xiao Wen, Dipto Thakurta, Manish Sharma, Daniel Murray
  • Publication number: 20240329122
    Abstract: A device under test (DUT) structure for voltage contrast (VC) detection of contact opens comprises a fin formed along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: Sairam SUBRAMANIAN, Amit PALIWAL, Xiao WEN, Dipto THAKURTA
  • Publication number: 20240112962
    Abstract: Embodiments disclosed herein include an apparatus for alignment detection. In an embodiment, the apparatus comprises a substrate, and a plurality of devices on the substrate, where each of the plurality of devices comprises a process monitor structure with different offsets from a target value. In an embodiment, a plurality of electrically conductive traces are on the substrate, where each of the plurality of electrically conductive traces has a first end and a second end opposite the first end, and where each of the plurality of electrically conductive traces is electrically coupled at the first end, respectively, with each of the plurality of devices. In an embodiment, the second end of the each of the plurality of electrical traces is within a scan area on the substrate, and where the each of the plurality of electrically conductive traces are not directly electrically coupled with each other.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Xiao WEN, Dipto THAKURTA, Sairam SUBRAMANIAN, David SANCHEZ, Amit PALIWAL
  • Publication number: 20240006254
    Abstract: Embodiments described herein may be related to apparatuses, systems, processes, and/or techniques for identifying device defects on a wafer substrate using voltage contrast techniques and electronic beam scans by scanning an area on a portion of the wafer that includes ends of a plurality of traces that extend from the scan area respectively to blocks on the wafer that include devices to be tested. During the electronic beam scan, ends of the plurality of traces within the scan area that are coupled with devices that are electrically shorted will appear bright, and those that are electrically open will appear dark. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Xiao WEN, Dipto THAKURTA, Sairam SUBRAMANIAN
  • Publication number: 20240006501
    Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for electrically coupling components of a transistor structure together in order to perform a voltage contrast test to determine opens and shorts within the transistor structure. In embodiments, trench contacts (TCN) within a transistor structure may be electrically coupled together with an electrical connection that is electrically isolated from a power rail. In other embodiments, TCN may be electrically coupled using P-type epitaxial layers on a P-type substrate. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Xiao WEN, Dipto THAKURTA, Sairam SUBRAMANIAN, Manish SHARMA