Patents by Inventor Dirk Ahlers

Dirk Ahlers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183445
    Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: November 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Frank Daeche, Daniel Schleisser, Thomas Stoek
  • Publication number: 20210358836
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Patent number: 11101201
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Patent number: 10957686
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor. A method of producing the semiconductor device is also described.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Patent number: 10879384
    Abstract: An alternator assembly includes an input terminal configured to input an alternating voltage, an output terminal configured to output a rectified voltage, and a gated diode arranged in a load path between the input terminal and the output terminal.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 29, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Markus Zundel, Dietrich Bonart, Ludger Borucki
  • Publication number: 20200279795
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Publication number: 20200279799
    Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.
    Type: Application
    Filed: January 29, 2020
    Publication date: September 3, 2020
    Inventors: Dirk AHLERS, Frank DAECHE, Daniel SCHLEISSER, Thomas STOEK
  • Patent number: 10700061
    Abstract: A semiconductor device includes a first transistor and a second transistor in a semiconductor substrate. The first transistor includes a first drain contact electrically connected to a first drain region, the first drain contact including a first drain contact portion and a second drain contact portion. The first drain contact portion includes a drain conductive material in direct contact with the first drain region. The second transistor includes a second source contact electrically connected to a second source region. The second source contact includes a first source contact portion and a second source contact portion. The first source contact portion includes a source conductive material in direct contact with the second source region.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Dirk Ahlers, Till Schloesser
  • Publication number: 20200183056
    Abstract: A power semiconductor module includes a first substrate, wherein the first substrate includes aluminum, a first aluminum oxide layer arranged on the first substrate, a conductive layer arranged on the first aluminum oxide layer, a first semiconductor chip, wherein the first semiconductor chip is arranged on the conductive layer and is electrically connected thereto, and an electrical insulation material enclosing the first semiconductor chip, wherein the first aluminum oxide layer is configured to electrically insulate the first semiconductor chip from the first substrate.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 11, 2020
    Inventors: Ivan Nikitin, Dirk Ahlers, Andreas Grassmann, Andre Uhlemann
  • Publication number: 20200152621
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Patent number: 10586792
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Patent number: 10319671
    Abstract: A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 11, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Gilles Delarozee, Daniel Schleisser, Christopher Spielman, Thomas Stoek
  • Publication number: 20190157259
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Application
    Filed: December 31, 2018
    Publication date: May 23, 2019
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Patent number: 10291108
    Abstract: A rectifying device includes a power transistor, a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: May 14, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Frank Auer, Herbert Gietler, Michael Lenz
  • Patent number: 10276706
    Abstract: A gated diode in a press-fit housing includes a base configured to be press-fit into an opening of a diode carrier plate and including a pedestal portion with a first flat surface, and a head wire including a head portion with a second flat surface and a wire portion. The base and the head wire form parts of the press-fit housing. The gated diode in the press-fit housing further includes a semiconductor die, a first solder layer engaging and electrically connecting the semiconductor die with the first flat surface of the base, and a second solder layer engaging and electrically connecting the semiconductor die with the second flat surface of the head wire.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Markus Zundel, Dietrich Bonart, Ludger Borucki
  • Publication number: 20190109226
    Abstract: An alternator assembly includes an input terminal configured to input an alternating voltage, an output terminal configured to output a rectified voltage, and a gated diode arranged in a load path between the input terminal and the output terminal.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 11, 2019
    Inventors: Dirk Ahlers, Markus Zundel, Dietrich Bonart, Ludger Borucki
  • Patent number: 10186508
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Publication number: 20180342447
    Abstract: A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 29, 2018
    Inventors: Dirk Ahlers, Gilles Delarozee, Daniel Schleisser, Christopher Spielman, Thomas Stoek
  • Patent number: 9978672
    Abstract: A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Gilles Delarozee, Daniel Schleisser, Christopher Spielman, Thomas Stoek
  • Publication number: 20180114788
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 26, 2018
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann