Abstract: Integrated circuits comprising an EEPROM require a large amount of time for testing, because the write time for a memory cell is very long. Notably the first test after manufacture, with the circuit still present on the wafer, is time consuming. The invention proposes a drastic reduction of the duration of the first test after manufacture by supplying a number of integrated circuits with a voltage in parallel and by providing each integrated circuit with an element whereby several block-wise write cycles for alternately "0" and "1" are executed in substantially autonomously and at the end of the first test step predetermined information is retained. This step is followed by a thermal treatment, after which the integrated circuits are individually contacted and first tested for information retention.

Abstract: Prepaid smart cards which serve to procure services, for example from a public telephone, comprise a memory for value units which are debited in conformity with the service procured, i.e. are marked as having been consumed. The smart card comprises a test code circuit which generates reply data from a supplied test word in conformity with a secret algorithm. Upon use of the smart card it is thus checked whether a valid smart card is concerned. Fraud could be attempted by using a valid smart card and a test code circuit present therein in combination with a separate, manipulatable memory. In order to prevent this, the algorithm of the test code circuit is modified in dependence on the contents of the memory of the valid smart card, the smart card being checked by means of the test code circuit at least after the debiting of value units. Fraudulent use of an external memory is thus no longer possible.