Patents by Inventor Dirk Breuer
Dirk Breuer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230238336Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Inventors: Ranjan RAJOO, Frank G. KUECHENMEISTER, Dirk BREUER
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Patent number: 11652069Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.Type: GrantFiled: December 8, 2020Date of Patent: May 16, 2023Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ranjan Rajoo, Frank G. Kuechenmeister, Dirk Breuer
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Publication number: 20220181271Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventors: Ranjan RAJOO, Frank G. KUECHENMEISTER, Dirk BREUER
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Patent number: 11127674Abstract: Disclosed are embodiments of a back end of the line (BEOL) metal structure that includes, within a metal level, a metal via, which has at least eight sides and all interior angles at 135° or more, and a metal wire thereon. The metal wire and via include respective portions of a continuous conformal metal layer. A passivation layer coats the top surface of the metal layer. The metal via and the metal wire thereon can be in an upper metal level and can be made of one metal (e.g., aluminum or an aluminum alloy). The upper metal level can be above a lower metal level that similarly includes a metal via and metal wire thereon, but the metal used can be different (e.g., copper) and/or the shape of the via can be different (e.g., four-sided). Also disclosed herein are method embodiments for forming the above-described BEOL metal structure.Type: GrantFiled: October 16, 2019Date of Patent: September 21, 2021Assignee: GlobalFoundries U.S. Inc.Inventors: Dirk Breuer, Oliver M. Witnik, Carla Byloos, Holger S. Schuehrer
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Patent number: 11105846Abstract: Embodiments of the disclosure provide a system for detecting and monitoring a crack in an integrated circuit (IC), including: at least one electrically conductive perimeter line (PLINE) extending about, and electrically isolated from, a protective structure formed in an inactive region of the IC, wherein an active region of the IC is enclosed within the protective structure; a circuit for sensing a change in an electrical characteristic of the at least one PLINE, the change in the electrical characteristic indicating a presence of a crack in the inactive region of the IC; and a connecting structure for electrically coupling each PLINE to the sensing circuit.Type: GrantFiled: April 2, 2020Date of Patent: August 31, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Nicholas A. Polomoff, Dirk Breuer, Eric D. Hunt-Schroeder, Bernhard J Wunder, Dewei Xu
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Publication number: 20210118796Abstract: Disclosed are embodiments of a back end of the line (BEOL) metal structure that includes, within a metal level, a metal via, which has at least eight sides and all interior angles at 135° or more, and a metal wire thereon. The metal wire and via include respective portions of a continuous conformal metal layer. A passivation layer coats the top surface of the metal layer. The metal via and the metal wire thereon can be in an upper metal level and can be made of one metal (e.g., aluminum or an aluminum alloy). The upper metal level can be above a lower metal level that similarly includes a metal via and metal wire thereon, but the metal used can be different (e.g., copper) and/or the shape of the via can be different (e.g., four-sided). Also disclosed herein are method embodiments for forming the above-described BEOL metal structure.Type: ApplicationFiled: October 16, 2019Publication date: April 22, 2021Applicant: GLOBALFOUNDRIES U.S. INC.Inventors: Dirk Breuer, Oliver M. Witnik, Carla Byloos, Holger S. Schuehrer
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Patent number: 10607947Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.Type: GrantFiled: June 4, 2018Date of Patent: March 31, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Dirk Breuer, Maik Liebau, Matthias Lehr
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Patent number: 10340229Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.Type: GrantFiled: October 11, 2017Date of Patent: July 2, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Dirk Breuer, Georg Talut
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Publication number: 20190109097Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.Type: ApplicationFiled: October 11, 2017Publication date: April 11, 2019Inventors: Dirk Breuer, Georg Talut
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Publication number: 20180286773Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.Type: ApplicationFiled: June 4, 2018Publication date: October 4, 2018Inventors: Dirk Breuer, Maik Liebau, Matthias Lehr
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Patent number: 10014234Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.Type: GrantFiled: December 2, 2016Date of Patent: July 3, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Dirk Breuer, Maik Liebau, Matthias Lehr
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Publication number: 20180158745Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.Type: ApplicationFiled: December 2, 2016Publication date: June 7, 2018Inventors: Dirk Breuer, Maik Liebau, Matthias Lehr
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Patent number: 9021894Abstract: Generally, the subject matter herein relates to detecting the presence of weak BEOL sites in a metallization system. One disclosed method includes performing a lateral force test on a pillar bump formed above a metallization system of a semiconductor chip, which includes contacting the pillar bump with a test probe while moving the test probe at a substantially constant speed that is less than approximately 1 ?m/sec along a path that is oriented at a substantially non-zero angle relative to a plane of the metallization system. Furthermore, the test probe is moving substantially away from the metallization system so that a force imposed on the pillar bump by the test probe has an upward component that induces a tensile load on the metallization system. The disclosed method also includes determining a behavioral interaction between the pillar bump and the metallization system during the lateral force test.Type: GrantFiled: July 27, 2012Date of Patent: May 5, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
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Patent number: 8957524Abstract: One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the upper portion has a second lateral dimension that is less than the first lateral dimension. A method disclosed herein of forming a pillar includes forming a base such that it is conductively coupled to a bond pad on an integrated circuit product and, after forming the base, forming an upper portion such that it is conductively coupled to the base.Type: GrantFiled: March 15, 2013Date of Patent: February 17, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Dirk Breuer, Frank Kuechenmeister, Jens Paul, Kashi Vishwanath Machani
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Patent number: 8950269Abstract: Generally, the subject matter disclosed herein relates to testing pillar bumps formed on a semiconductor chip so as to detect the presence of anomalous stiff pillar bumps. One illustrative method disclosed herein includes positioning a test probe adjacent to a side of a pillar bump formed above a metallization system of a semiconductor chip, and performing a lateral force test on the pillar bump by contacting the side of the pillar bump with the test probe while moving the test probe at a substantially constant speed that is less than approximately 1 ?m/sec.Type: GrantFiled: July 27, 2012Date of Patent: February 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
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Publication number: 20140264890Abstract: One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the upper portion has a second lateral dimension that is less than the first lateral dimension. A method disclosed herein of forming a pillar includes forming a base such that it is conductively coupled to a bond pad on an integrated circuit product and, after forming the base, forming an upper portion such that it is conductively coupled to the base.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Dirk Breuer, Frank Kuechenmeister, Jens Paul, Kashi Vishwanath Machani
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Patent number: 8829675Abstract: A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches.Type: GrantFiled: November 19, 2013Date of Patent: September 9, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
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Publication number: 20140077368Abstract: A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches.Type: ApplicationFiled: November 19, 2013Publication date: March 20, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
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Publication number: 20140027902Abstract: Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
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Publication number: 20140026676Abstract: Generally, the subject matter herein relates to detecting the presence of weak BEOL sites in a metallization system. One disclosed method includes performing a lateral force test on a pillar bump formed above a metallization system of a semiconductor chip, which includes contacting the pillar bump with a test probe while moving the test probe at a substantially constant speed that is less than approximately 1 ?m/sec along a path that is oriented at a substantially non-zero angle relative to a plane of the metallization system. Furthermore, the test probe is moving substantially away from the metallization system so that a force imposed on the pillar bump by the test probe has an upward component that induces a tensile load on the metallization system. The disclosed method also includes determining a behavioral interaction between the pillar bump and the metallization system during the lateral force test.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer