Patents by Inventor Dirk Drescher

Dirk Drescher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6960541
    Abstract: A semiconductor element with at least one layer of tungsten oxide, optionally in a structured tungsten oxide layer, is described. The semiconductor element is characterized in that the relative premittivity of the tungsten oxide layer is higher than 50.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: November 1, 2005
    Assignee: Infineon Technologies AG
    Inventors: Dirk Drescher, Helmut Tews, Martin Schrems, Helmut Wurzer
  • Patent number: 6781180
    Abstract: A trench capacitor for use in a semiconductor memory cell is formed in a substrate and includes a trench having an upper region and a lower region. An insulation collar is formed in the upper region of the trench. The lower region of the trench extends through a buried well. A dielectric layer, which is formed from tungsten oxide, serves as a capacitor dielectric. A conductive trench filling, which is filled into the trench, is formed from silicon or a tungsten-containing material such as tungsten, tungsten silicide or tungsten nitride.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: August 24, 2004
    Assignee: Infineon Technologies AG
    Inventors: Schrems Martin, Dirk Drescher, Helmut Wurzer, Wolfram Karcher
  • Patent number: 6693022
    Abstract: Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: February 17, 2004
    Assignee: Infineon Technologies AG
    Inventors: Joerg Dreybrodt, Dirk Drescher, Ralf Zedlitz, Stephan Wege
  • Publication number: 20030017684
    Abstract: Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.
    Type: Application
    Filed: August 23, 2002
    Publication date: January 23, 2003
    Applicant: Infineon Technologies AG
    Inventors: Joerg Dreybrodt, Dirk Drescher, Ralf Zedlitz, Stephan Wege
  • Patent number: 6479373
    Abstract: Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing, gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: November 12, 2002
    Assignee: Infineon Technologies AG
    Inventors: Joerg Dreybrodt, Dirk Drescher, Ralf Zedlitz, Stephan Wege
  • Publication number: 20020070414
    Abstract: A semiconductor element with at least one layer of tungsten oxide, optionally in a structured tungsten oxide layer, is described. The semiconductor element is characterized in that the relative premittivity of the tungsten oxide layer is higher than 50.
    Type: Application
    Filed: July 16, 2001
    Publication date: June 13, 2002
    Inventors: Dirk Drescher, Helmut Tews, Martin Schrems, Helmut Wurzer
  • Publication number: 20020016044
    Abstract: Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.
    Type: Application
    Filed: June 19, 2001
    Publication date: February 7, 2002
    Inventors: Joerg Dreybrodt, Dirk Drescher, Ralf Zedlitz, Stephan Wege
  • Publication number: 20020000634
    Abstract: The connection element in an integrated circuit has a layer structure arranged between two conductive structures. The layer structure has a dielectric layer which can be destroyed by application of a predetermined voltage. At least one conductive structure is composed of tungsten. The conductive structure adjoins a conductive layer made of tungsten or a tungsten compound, which is a constituent part of the layer structure and which adjoins the dielectric layer.
    Type: Application
    Filed: June 22, 2001
    Publication date: January 3, 2002
    Inventors: Dirk Drescher, Wolfgang Leiberg, Rene Tews, Matthias Lehr, Alexander Ruf