Patents by Inventor Dirk Efferenn

Dirk Efferenn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7413993
    Abstract: The invention is concerned with a process for removing residue comprising a polymeric resist and metal oxide from a metal structure on a semiconductor substrate, the process comprising the steps of: (a) heating up the substrate with the metal structure in the presence of molecular nitrogen gas (N2); (b) a stabilization step in the presence of pure molecular nitrogen gas (N2); (c) a passivation step employing a plasma containing at least one of the group of water, nitrogen and oxygen; and (d) a stripping step containing oxygen to remove the residue, comprising resist.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: August 19, 2008
    Assignees: Infineon Technologies AG, Nanya Technology Corporation
    Inventors: Ronald Gottzein, Jens Bachmann, Dirk Efferenn, Uwe Kahler, Chung-Hsin Lin, Wen-Bin Lin, Lee Donohue
  • Patent number: 7261829
    Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Dirk Efferenn, Hans-Peter Moll
  • Patent number: 7157381
    Abstract: A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed; and structuring the whisker-free layer into the lines.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: January 2, 2007
    Assignees: Infineon Technologies AG, Nanya Technology Corporation
    Inventors: Dirk Efferenn, Jens Hahn, Uwe Kahler, Chung-Hsin Lin, Jens Bachmann, Wen-Bin Lin, Grit Bonsdorf
  • Patent number: 7125778
    Abstract: A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: October 24, 2006
    Assignee: Infineon Technologies AG
    Inventors: Dirk Efferenn, Ulrike Grüning Von Schwerin, Hans-Peter Moll, Jörg Radecker, Andreas Wich-Glasen
  • Publication number: 20060108324
    Abstract: The invention is concerned with a process for removing residue comprising a polymeric resist and metal oxide from a metal structure on a semiconductor substrate, the process comprising the steps of: (a) heating up the substrate with the metal structure in the presence of molecular nitrogen gas (N2); (b) a stabilization step in the presence of pure molecular nitrogen gas (N2); (c) a passivation step employing a plasma containing at least one of the group of water, nitrogen and oxygen; and (d) a stripping step containing oxygen to remove the residue, comprising resist.
    Type: Application
    Filed: November 22, 2004
    Publication date: May 25, 2006
    Inventors: Ronald Gottzein, Jens Bachmann, Dirk Efferenn, Uwe Kahler, Chung-Hsin Lin, Wen-Bin Lin, Lee Donohue
  • Publication number: 20050277300
    Abstract: A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed; and structuring the whisker-free layer into the lines.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 15, 2005
    Inventors: Dirk Efferenn, Jens Hahn, Uwe Kahler, Chung-Hsin Lin, Jens Bachmann, Wen-Bin Lin, Grit Bonsdorf
  • Patent number: 6964912
    Abstract: A method for fabricating a semiconductor structure includes providing a semiconductor substrate, providing a plurality of trenches in the semiconductor substrate using a first hard mask, and causing the hard mask to recede by a predetermined distance with respect to the trench wall at the top side of the semiconductor substrate for forming a first hard mask that has been caused to recede. An isolation trench structure is provided in the semiconductor substrate using a second hard mask, the isolation trench structure subdividing the first first hard mask that has been caused to recede along rows into strip sections and the strip sections of adjacent rows being arranged offset with respect to one another. The receding process results in a reduction of an overlap region between two strip sections of adjacent rows in comparison with an overlap region which would be present without the receding process.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: November 15, 2005
    Assignee: Infineon Technologies AG
    Inventors: Dirk Efferenn, Hans-Peter Moll
  • Publication number: 20050224451
    Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.
    Type: Application
    Filed: January 8, 2003
    Publication date: October 13, 2005
    Inventors: Dirk Efferenn, Hans-Peter Moll
  • Publication number: 20040157390
    Abstract: The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (10); providing a plurality of trenches (G11, G12; G21) in the semiconductor substrate (10) using a first hard mask (50), which trenches are arranged offset with respect to one another in rows (r1, r2) and columns (s1, s2, s3); causing the hard mask (50) to recede by a predetermined distance (&Dgr;) with respect to the trench wall at the top side (OS) of the semiconductor substrate (10) for the purpose of forming a first hard mask (50′) that has been caused to recede; providing an isolation trench structure (ST) in the semiconductor substrate (10) using a second hard mask (HM), the isolation trench structure (ST) subdividing the first first [sic] hard mask (50′) that has been caused to recede along the rows (r1, r2) into strip sections (501′, 502′; 503′) and the strip sections (501′; 503′) of adjacent rows (r1, r2) being
    Type: Application
    Filed: November 26, 2003
    Publication date: August 12, 2004
    Applicant: Infineon Technologies AG
    Inventors: Dirk Efferenn, Hans-Peter Moll
  • Patent number: 6770530
    Abstract: The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: August 3, 2004
    Assignee: Infineon Technologies AG
    Inventors: Dirk Efferenn, Hans-Peter Moll, Andreas Wich-Glasen
  • Patent number: 6716720
    Abstract: A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of an isolation trench formation. A covering layer, preferably made of silicon oxide, is deposited in a large-area manner and is then doped with doping material, preferably nitrogen, essentially right over the entire depth of the layer. The doping material provides for an increased rate of removal of the covering layer, so that, after the removal process, the covering layer material only remains in the depressions.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: April 6, 2004
    Assignee: Infineon Technologies AG
    Inventors: Dirk Efferenn, Hans-Peter Moll
  • Publication number: 20030181019
    Abstract: The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.
    Type: Application
    Filed: March 10, 2003
    Publication date: September 25, 2003
    Inventors: Dirk Efferenn, Hans-Peter Moll, Andreas Wich-Glasen
  • Publication number: 20030166327
    Abstract: A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of an isolation trench formation. A covering layer, preferably made of silicon oxide, is deposited in a large-area manner and is then doped with doping material, preferably nitrogen, essentially right over the entire depth of the layer. The doping material provides for an increased rate of removal of the covering layer, so that, after the removal process, the covering layer material only remains in the depressions.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 4, 2003
    Inventors: Dirk Efferenn, Hans-Peter Moll
  • Publication number: 20030040184
    Abstract: A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.
    Type: Application
    Filed: August 27, 2002
    Publication date: February 27, 2003
    Inventors: Dirk Efferenn, Ulrike Gruning Von Schwerin, Hans-Peter Moll, Jorg Radecker, Andreas Wich-Glasen