Abstract: The present disclosure relates to circuit structures and, more particularly, to circuit structures which detect high speed and high precision characterization of VTsat and VTlin of FET arrays and methods of manufacture and use. The circuit includes a control loop comprised of a differential amplifier, a plurality of FET arrays, and at least one analog switch enabling selection between a calibration mode and an operation mode.

Abstract: The present disclosure relates to circuit structures and, more particularly, to circuit structures which detect high speed and high precision characterization of VTsat and VTlin of FET arrays and methods of manufacture and use. The circuit includes a control loop comprised of a differential amplifier, a plurality of FET arrays, and at least one analog switch enabling selection between a calibration mode and an operation mode.

Abstract: Methods and systems are provided for computing IR drop, i.e., voltage drop, in a semiconductor device. The method includes generating a modeling element corresponding to the plurality of transistors. At least one of the transistors in the modeling element is replaced with a current source. The method also includes performing an IR drop analysis of the modeling element utilizing a software program to calculate the IR drop in the semiconductor device.

Abstract: A device includes a substrate and a dual port static random access memory cell. The substrate includes an N-well region, a first P-well region and a second P-well region. The first and second P-well regions are arranged on opposite sides of the N-well region and spaced apart along a width direction. The static random access memory cell includes first and second pull-up transistors that are provided in the N-well region, a first pair of pull-down transistors and a first pair of access transistors provided in the first P-well region, and a second pair of pull-down transistors and a second pair of access transistors provided in the second P-well region. Each of the first pair and the second pair of pull-down transistors includes a first pull-down transistor and a second pull-down transistor. Active regions of the first pull-down transistor and the second pull-down transistor are spaced apart along the width direction.

Abstract: A device includes a substrate and a dual port static random access memory cell. The substrate includes an N-well region, a first P-well region and a second P-well region. The first and second P-well regions are arranged on opposite sides of the N-well region and spaced apart along a width direction. The static random access memory cell includes first and second pull-up transistors that are provided in the N-well region, a first pair of pull-down transistors and a first pair of access transistors provided in the first P-well region, and a second pair of pull-down transistors and a second pair of access transistors provided in the second P-well region. Each of the first pair and the second pair of pull-down transistors includes a first pull-down transistor and a second pull-down transistor. Active regions of the first pull-down transistor and the second pull-down transistor are spaced apart along the width direction.

Abstract: Methods and systems are provided for computing IR drop, i.e., voltage drop, in a semiconductor device. The method includes generating a modeling element corresponding to the plurality of transistors. At least one of the transistors in the modeling element is replaced with a current source. The method also includes performing an IR drop analysis of the modeling element utilizing a software program to calculate the IR drop in the semiconductor device.

Abstract: In a sophisticated semiconductor device, a semiconductor-based electronic fuse may be formed in a bulk configuration, wherein the design and thus the configuration of the contact areas and the fuse region provide a wide programming window in terms of programming voltages and duration of the corresponding programming pulses.