Abstract: Because a customary data processing apparatus consisting of a program control section, an arithmetic and logic element and a data memory, also referred to as a microprocessor or microcontroller when integrated on a semiconductor chip, is temporarily not loaded by a control function in many applications, it is desirable to perform a plurality of such slow control functions by means of one apparatus. In order to achieve this as effectively as possible, in accordance with the invention there are added a sequencer and an address memory which is controlled by the sequencer and which takes up each time the next instruction address of a given control function or process which is each time associated with a sequence control signal. FOr the arithmetic and logic element there is preferably provided a buffer memory which is also controlled by the sequencer.