Abstract: A device (MAM) including a common data resource (RAM) to which a first (PR) and several second (LC) stations are coupled. This device includes a first transmission circuit (DB, MD, LD2, LD1, DBU) coupling the common resource and the first station and, for each of the second stations, a second transmission circuit (DB, MD) coupling the common resource and a buffer circuit (LR; LW) and a third transmission circuit (PISO, SO; SI, SIPO) coupling the buffer circuit and the corresponding second station and which is used at predetermined moments (T1, T2, T3; T4). The device also includes a priority circuit (CLC, SG) which grants the highest priority to the requests for the use of the first transmission circuit and the following priorities to the requests for the use of the second transmission circuits in decreasing order of the frequencies (SOS; SIS) of the corresponding predetermined moments.

Abstract: An amplifier includes two differential amplifiers which are connected to an output stage comprising two field effect transistors of opposite conductivity typed directly coupled in series between opposite poles of a DC voltage source. The junction between the two output transistors constitutes the output of the amplifier. A negative feedback loop connects the amplifier's output to the inputs of the differential amplifiers. A correction arrangement is provided to prevent excessive current consumption and cross-over distortion. Preferably, the correction arrangement uses a pair of current mirror circuits to generate respective measuring currents proportional to the current in each of the output transistors. Each such measuring current is compared with a reference current.

Abstract: Pulse Code Modulation (PCM) translator for translating a PCM input word into a PCM output word, one of said words being in accordance with a compressed code and the other with a linear code, characterized in that it is adapted to convert the binary bits of the input word into those of the output word in accordance with either the A-law or the mu-law. The circuit forms part of a telephone line circuit (LC) connected between a telephone line (LI) and a digital switching network (SNW) and comprising the cascade connection of a subscriber line interface (SLIC) able to perform line control and supervision, a digital signal processor (DSP) mainly adapted to execute analog-to-digital and digital-to-analog conversion operations, the above transcoder circuit and a dual processor terminal controller (DPTC) which deals with the general control of the line circuit. The DSP only processes linear PCM signals, whereas the DPTC solely operates on companded PCM signals.

Abstract: The present invention discloses a feedback control circuit in which the input and feedback signals are processed by making use of the same capacitance so that there is no problem of capacitance matching. Another aspect of the invention is a sigma-delta modulator in which the processing means includes integration means which are able to integrate said sampled and added input and feedback signals and to provide an analog output signal, a one-bit analog-to-digital converter providing a digital output signal in response to said analog output signal, and a one-bit digital-to-analog converter providing said feedback signal in response to said output signal, said input signal being sampled and simultaneously said converters being operated by and during first of said timing signals, while by and during second of said timing signals said feedback signal is sampled and said input and feedback signals are added and integrated, said first and second timing signals being non-overlapping and defining a sampling period.