Abstract: The invention provides a processing system, comprising a memory comprising a processor call stack; a stack space usage register configured to determine the stack space usage of the processor call stack and to store a usage parameter indicative of the determined stack space usage; a first threshold register configured to store a pre-determinable first stack level threshold; and a first comparator configured to compare the usage parameter with the first stack level threshold and to output a first interrupt blocking signal, if the usage parameter exceeds the first stack level threshold, the first interrupt blocking signal being configured to block the decoding of interrupt signals input to the processing system and having interrupt priorities lower than or equal to or just lower than a first interrupt priority threshold. The invention further provides a method for stack management, especially in a processing system.

Abstract: A protection unit of an interrupt stack accessible by a CPU controlled by one software program, for storing and removing stack frame(s), the stack protection unit being coupleable to the stack and the CPU, comprising: a processor coupled to a first and a second address register; wherein, when a first stack frame is stored onto the stack and the execution of the software program is suspended by the CPU, responsive to one or more occurring hardware IRQs; the processing unit is adapted to set one access rule based on the first and second address registers, preventing: the occurring ISR to be serviced, from accessing a hardware-protected region of the stack, comprising at least the first stack frame and at least one stack frame associated with one or more suspended IRQs. A processor, a method and a computer program are also claimed.

Abstract: The present application relates to a flash memory controller and a method of operating thereof. A system bus interface is provided to interface with a system bus and a debug bus interface is provided to interface with a debug bus. A flash access control block is provided to perform storage I/O operations on a flash memory array. A debug control block is provided to monitor debug related information. The flash memory controller is configured to selectively operate in one or storage operating mode or debug operating mode. In the debug operating mode: the storage control block is configured to serve only read data access requests; and the debug control block is configured to store trace messages in an allocated part of the storage resources of the flash memory controller in response to trace events. The trace messages are generated on the basis of the monitored debug related information.

Abstract: Electronic device packages and related fabrication methods are provided. An exemplary electronic device includes a semiconductor die having debug circuitry fabricated thereon, a framing structure including an interior portion having the semiconductor die mounted thereto, and a conductive element providing an electrical connection between the interior portion and a contact pad on the semiconductor die that corresponds or is otherwise coupled to an interface of the debug circuitry.

Abstract: The present application relates to a flash memory controller and a method of operating thereof. A system bus interface is provided to interface with a system bus and a debug bus interface is provided to interface with a debug bus. A flash access control block is provided to perform storage I/O operations on a flash memory array. A debug control block is provided to monitor debug related information. The flash memory controller is configured to selectively operate in one or storage operating mode or debug operating mode. In the debug operating mode: the storage control block is configured to serve only read data access requests; and the debug control block is configured to store trace messages in an allocated part of the storage resources of the flash memory controller in response to trace events. The trace messages are generated on the basis of the monitored debug related information.

Abstract: Electronic device packages and related fabrication methods are provided. An exemplary electronic device includes a semiconductor die having debug circuitry fabricated thereon, a framing structure including an interior portion having the semiconductor die mounted thereto, and a conductive element providing an electrical connection between the interior portion and a contact pad on the semiconductor die that corresponds or is otherwise coupled to an interface of the debug circuitry.

Abstract: The invention provides a processing system, comprising a memory comprising a processor call stack; a stack space usage register configured to determine the stack space usage of the processor call stack and to store a usage parameter indicative of the determined stack space usage; a first threshold register configured to store a pre-determinable first stack level threshold; and a first comparator configured to compare the usage parameter with the first stack level threshold and to output a first interrupt blocking signal, if the usage parameter exceeds the first stack level threshold, the first interrupt blocking signal being configured to block the decoding of interrupt signals input to the processing system and having interrupt priorities lower than or equal to or just lower than a first interrupt priority threshold. The invention further provides a method for stack management, especially in a processing system.

Abstract: A method and apparatus for storing trace data within a processing system. The method includes configuring at least one Error Correction Code, ECC, component within the processing system to operate in a trace data storage operating mode, generating trace data at a debug module of the processing system, and conveying the trace data from the debug module to the at least one ECC component for storing in an area of memory used for ECC information.

Abstract: A processing device and a method of executing an instruction sequence are described. The processing device comprises a status register for providing a status word, wherein execution of an instruction by the processing device comprises updating the status word, wherein the instruction sequence comprises a subsequence of one or more selected instructions, and wherein execution of a selected instruction by the processing device further comprises a status check which comprises: providing a set of valid status words; verifying whether the updated status word is in the set of valid status words; and initiating an alert action if the updated status word is not in the set of valid status words.

Abstract: A protection unit of a subroutine stack accessible by a CPU controlled by one main software program, for storing and removing stack frame(s), the stack protection unit being coupleable to the stack and the CPU, comprising: a processor coupled to a first and a second address register; wherein, when a first stack frame is stored onto the stack and the execution of the main software program is suspended by the CPU due to the execution of a subroutine; the processing unit is adapted to set one access rule based on the first and second address registers, preventing: the ongoing subroutine, from accessing a hardware-protected region of the stack, comprising at least one stack frame associated with a return address from which the main software program resumes execution after termination of the execution of the subroutine. A processor, a method and a computer program are also claimed.

Abstract: A method for protecting a data item against unauthorized access and a data processing device is disclosed comprising a memory unit and a memory control unit to protect data items stored in the memory unit against prohibited access. Upon a write access the memory control unit forms a first data word comprising a data item and a first key; computes a first error-detection code; and stores the data item along with the first error-detection code. Upon a read access the memory control unit reads the data item and the first error-detection code; forms a second data word comprising the data item and a second key; computes a second error-detection code to the second data word; and determines a syndrome on the basis of the first error-detection code and the second error-detection code, wherein the syndrome is indicative of whether or not the first and second data words are identical.

Abstract: A method for protecting a data item against unauthorized access and a data processing device is disclosed comprising a memory unit and a memory control unit to protect data items stored in the memory unit against prohibited access. Upon a write access the memory control unit forms a first data word comprising a data item and a first key; computes a first error-detection code; and stores the data item along with the first error-detection code. Upon a read access the memory control unit reads the data item and the first error-detection code; forms a second data word comprising the data item and a second key; computes a second error-detection code to the second data word; and determines a syndrome on the basis of the first error-detection code and the second error-detection code, wherein the syndrome is indicative of whether or not the first and second data words are identical.

Abstract: A processing device, comprising one or more functional units and a hardware-serviced watchdog timer connected to the functional units is described. The functional units are capable of generating service events which are hardware events of said one or more functional units. The functional units are arranged to generate the signals in response to an application executed on the processing device and making use of the functionality thereof. The watchdog timer is arranged to start a new timeout period in response to any one of said signals. The service events may include, for example, a start or an end of a data transfer operation to or from one of the functional units. A method of operating a processing device is described as well.

Abstract: A processing device and a method of executing an instruction sequence are described. The processing device comprises a status register for providing a status word, wherein execution of an instruction by the processing device comprises updating the status word, wherein the instruction sequence comprises a subsequence of one or more selected instructions, and wherein execution of a selected instruction by the processing device further comprises a status check which comprises: providing a set of valid status words; verifying whether the updated status word is in the set of valid status words; and initiating an alert action if the updated status word is not in the set of valid status words.

Abstract: A protection unit of a subroutine stack accessible by a CPU controlled by one main software program, for storing and removing stack frame(s), the stack protection unit being coupleable to the stack and the CPU, comprising: a processor coupled to a first and a second address register; wherein, when a first stack frame is stored onto the stack and the execution of the main software program is suspended by the CPU due to the execution of a subroutine; the processing unit is adapted to set one access rule based on the first and second address registers, preventing: the ongoing subroutine, from accessing a hardware-protected region of the stack, comprising at least one stack frame associated with a return address from which the main software program resumes execution after termination of the execution of the subroutine. A processor, a method and a computer program are also claimed.

Abstract: A protection unit of an interrupt stack accessible by a CPU controlled by one software program, for storing and removing stack frame(s), the stack protection unit being coupleable to the stack and the CPU, comprising: a processor coupled to a first and a second address register; wherein, when a first stack frame is stored onto the stack and the execution of the software program is suspended by the CPU, responsive to one or more occurring hardware IRQs; the processing unit is adapted to set one access rule based on the first and second address registers, preventing: the occurring ISR to be serviced, from accessing a hardware-protected region of the stack, comprising at least the first stack frame and at least one stack frame associated with one or more suspended IRQs. A processor, a method and a computer program are also claimed.

Abstract: A method and apparatus for storing trace data within a processing system. The method comprises configuring at least one Error Correction Code, ECC, component within the processing system to operate in a trace data storage operating mode, generating trace data at a debug module of the processing system, and conveying the trace data from the debug module to the at least one ECC component for storing in an area of memory used for ECC information.