Abstract: A method for operating an integrated memory unit having a memory cell field includes the steps of, before a memory access, partitioning the memory cell field into a plurality of memory areas, for memory access, selecting one of the memory areas through the application of a memory area address, during the memory access, and internally generating addresses for access to memory cells of the one of the memory areas by the memory unit. Through a common external terminal connection of the memory unit, the memory area addresses are transmitted, and, subsequently, access data of the one of the memory areas are transmitted successively. The operating method enables a comparatively low number of terminal tendons.

Abstract: A semiconductor memory has a data signal path and a control device in order to supply functional elements of the data signal path with control signals. Programmable delays are connected into the signal lines providing the control signals, so that the time relationships between the control signals can be set reversibly via a soft set register or irreversibly via fuses. This enables simple adaptation of the internal control signal timing to fluctuations in the fabrication process or after conversion of the configuration to a new fabrication process.

Abstract: An integrated memory having a memory cell array with addressable column lines and addressable row lines is described. The memory further has a charge equalization device for charge equalization on the column lines, and an amplifier circuit connected to the column lines. A control device drives the charge equalization device after the activation of an addressed row line for writing to a memory cell, so that charge equalization is carried out on an addressed column line. Furthermore, the control device is connected to the amplifier circuits to switch the amplifier circuits on and off. After the activation of the addressed row line, the amplifier circuit on the addressed column line is switched off during a write procedure. Afterward, the charge potential on the addressed column line is equalized by the charge equalization device. Afterward, the amplifier device is switched on for writing the datum to the addressed memory cell.

Abstract: The method and the device are particularly suitable for data exchange between memory modules and logic modules. A multidigit digital signal at the transmitter end is converted into a corresponding analog signal by a D/A converter. The analog signal is transferred via a transfer line and the analog signal received at the transmitter end is converted back into a digital signal identical to the digital signal of the transmitter end with an A/D converter. An A/D converter based on the principle of successive approximation is used at the receiver end. The converter has a calibration circuit which, during a calibration cycle, by way of an additional “overdrive” transistor and a register, varies gate voltages of the transistors used for decoding purposes until the output signal of a comparator disappears.

Abstract: A data driver is activated in dependence of a provided bit sequence in order to produce, at the data output of the driver, a data signal which, in the times between periodic reference clock pulse edges, is in each case driven to a high or low validity level in accordance with the binary value of the bits of the provided bit sequence. Directly before selected reference clock pulse edges, a preparation interval of a fixed length is provided, during which the driver is prompted to drive its data output to a medium level between the high validity level and the low validity level. The length of the preparation interval is at least equal to the response time necessary to drive the data output over the level difference between one of the validity levels and the medium level, but is shorter than twice this response time.

Abstract: A semiconductor memory has a data signal path and a control device in order to supply functional elements of the data signal path with control signals. Programmable delays are connected into the signal lines providing the control signals, so that the time relationships between the control signals can be set reversibly via a soft set register or irreversibly via fuses. This enables simple adaptation of the internal control signal timing to fluctuations in the fabrication process or after conversion of the configuration to a new fabrication process.

Abstract: A method for operating an integrated memory unit having a memory cell field includes the steps of, before a memory access, partitioning the memory cell field into a plurality of memory areas, for memory access, selecting one of the memory areas through the application of a memory area address, during the memory access, and internally generating addresses for access to memory cells of the one of the memory areas by the memory unit. Through a common external terminal connection of the memory unit, the memory area addresses are transmitted, and, subsequently, access data of the one of the memory areas are transmitted successively. The operating method enables a comparatively low number of terminal tendons.

Abstract: An integrated memory having a memory cell array with addressable column lines and addressable row lines is described. The memory further has a charge equalization device for charge equalization on the column lines, and an amplifier circuit connected to the column lines. A control device drives the charge equalization device after the activation of an addressed row line for writing to a memory cell, so that charge equalization is carried out on an addressed column line. Furthermore, the control device is connected to the amplifier circuits to switch the amplifier circuits on and off. After the activation of the addressed row line, the amplifier circuit on the addressed column line is switched off during a write procedure. Afterward, the charge potential on the addressed column line is equalized by the charge equalization device. Afterward, the amplifier device is switched on for writing the datum to the addressed memory cell.

Abstract: A data driver is activated in dependence of a provided bit sequence in order to produce, at the data output of the driver, a data signal which, in the times between periodic reference clock pulse edges, is in each case driven to a high or low validity level in accordance with the binary value of the bits of the provided bit sequence. Directly before selected reference clock pulse edges, a preparation interval of a fixed length is provided, during which the driver is prompted to drive its data output to a medium level between the high validity level and the low validity level. The length of the preparation interval is at least equal to the response time necessary to drive the data output over the level difference between one of the validity levels and the medium level, but is shorter than twice this response time.

Abstract: The method and the device are particularly suitable for data exchange between memory modules and logic modules. A multidigit digital signal at the transmitter end is converted into a corresponding analog signal by a D/A converter. The analog signal is transferred via a transfer line and the analog signal received at the transmitter end is converted back into a digital signal identical to the digital signal of the transmitter end with an A/D converter. An A/D converter based on the principle of successive approximation is used at the receiver end. The converter has a calibration circuit which, during a calibration cycle, by way of an additional “overdrive” transistor and a register, varies gate voltages of the transistors used for decoding purposes until the output signal of a comparator disappears.