Abstract: The invention relates to the manufacture of a semiconductor device (10) with a semiconductor body (1) and a substrate (2) and comprising at least one semiconductor element (3), which semiconductor device is equipped with at least one connection region (4) and a superjacent strip-shaped connection conductor (5) which is connected to the connection region, which connection region and connection conductor are both recessed in a dielectric, and a dielectric region (6) of a first material is provided on the semiconductor body (1) at the location of the connection region (4) to be formed, after which the dielectric region (6) is coated with a dielectric layer (7) of a second material that differs from the first material, which dielectric layer is provided, at the location of the strip-shaped connection conductor (5) to be formed, with a strip-shaped recess (7A) which overlaps the dielectric region (6) and extends up to said dielectric region, and after the formation of the recess (7A) and the removal of the dielect

Abstract: The invention relates to a method of manufacturing a semiconductor device, comprising the provision of a dual damascene structure (20). This dual damascene structure (20) comprises a metal layer (1) with thereon a first dielectric layer (2) provided with a via (3). A second dielectric layer (5) is applied on the first dielectric layer (2) and is provided with an interconnect groove (6). The via (3) and the interconnect groove (6) are filled with a metal which forms a metal lead (9) with a top (10). The method further comprises the following steps: removing the second dielectric layer (5), applying a disposable layer (12) to the first dielectric layer (2) and the metal lead (9), planarizing the disposable layer (12) down to the top (10) of the metal lead (9), applying a porous dielectric layer (13) on the disposable layer (12), removing the disposable layer (12) through the porous dielectric layer (13) so as to form air gaps (14).

Abstract: The invention relates to a method of manufacturing a semiconductor device, comprising the provision of a dual damascene structure (20). This dual damascene structure (20) comprises a metal layer (1) with thereon a first dielectric layer (2) provided with a via (3). A second dielectric layer (5) is applied on the first dielectric layer (2) and is provided with an interconnect groove (6). The via (3) and the interconnect groove (6) are filled with a metal which forms a metal lead (9) with a top (10).