Abstract: This invention provides a switching converter having a number N of outputs providing N output signals, said switching converter being operable in at least a boost mode. The switching converter has at least one inductor, a number of switches, and a controlling device for controlling a charging time of the at least one inductor at least by the switches such that a discharging time of the at least one inductor is constant.

Abstract: This invention provides a switching converter having a plurality N of outputs providing N output signals and at least one inductor, comprising a first controlling device for controlling the total energy flowing over the inductor to the N outputs dependent on a first control signal, at least a second controlling device for distributing the total energy between the N outputs by means of at least a second control signal, wherein the first controlling device is coupled to all N outputs for receiving a number M of the respective feedback output signals of the N outputs, M?N, wherein the first controlling device comprises first means for weighting the M feedback output signals and second means for providing the first control signal dependent on the weighted M feedback output signals.

Abstract: Disclosed are systems and methods to achieve a low noise, fully differential amplifier with controlled common mode voltages at each stage output but without the requirement of a common mode feedback loop. Common mode voltages are adjusted by adjusting the currents flowing through the load impedances (bias currents) wherein the currents are derived from one or more voltage-to-current converters based on an impedance that matches to the load impedances of the stages of the amplifier. The amplifier invented is primarily used for amplification of low frequency signals. The amplifier has one or more gain stages applying only one conduction type of transistors of an IC technology that has the lowest transition frequency between 1/f noise and white noise to achieve a low chopping or autozeroing frequency.

Abstract: Disclosed are systems and methods to achieve a low noise, fully differential amplifier with controlled common mode voltages at each stage output but without the requirement of a common mode feedback loop. Common mode voltages are adjusted by adjusting the currents flowing through the load impedances (bias currents) wherein the currents are derived from one or more voltage-to-current converters based on an impedance that matches to the load impedances of the stages of the amplifier. The amplifier invented is primarily used for amplification of low frequency signals. The amplifier has one or more gain stages applying only one conduction type of transistors of an IC technology that has the lowest transition frequency between 1/f noise and white noise to achieve a low chopping or autozeroing frequency.

Abstract: A tracking analog-to-digital converter “ADC” with a self-controlled variable clock comprises: a digital register; a digital-to-analog converter “DAC” coupled to said digital register providing an analog feedback signal; a comparator coupled to an analog input signal and said analog feedback signal and providing a comparison signal based on a comparison between said analog input signal and said analog feedback signal, said comparison signal being coupled to the digital register; a means for determining comparator readiness to determine if said comparator is ready, indicating that said comparison signal can be reliably read, said means for determining comparator readiness further comprising a determination of a comparison ready indicator; a means for clocking to generate a clock signal to drive said digital register in response to said means for determining comparator readiness determining that said comparator is ready; and said digital register being configured to count in response to said clock signal based o

Abstract: A tracking analog-to-digital converter “ADC” with a self-controlled variable clock comprises: a digital register; a digital-to-analog converter “DAC” coupled to said digital register providing an analog feedback signal; a comparator coupled to an analog input signal and said analog feedback signal and providing a comparison signal based on a comparison between said analog input signal and said analog feedback signal, said comparison signal being coupled to the digital register; a means for determining comparator readiness to determine if said comparator is ready, indicating that said comparison signal can be reliably read, said means for determining comparator readiness further comprising a determination of a comparison ready indicator; a means for clocking to generate a clock signal to drive said digital register in response to said means for determining comparator readiness determining that said comparator is ready; and said digital register being configured to count in response to said clock signal based o

Abstract: This invention provides a switching converter having a number N of outputs providing N output signals, said switching converter being operable in at least a boost mode.

Abstract: This invention provides a switching converter having a plurality N of outputs providing N output signals and at least one inductor, comprising a first controlling device for controlling the total energy flowing over the inductor to the N outputs dependent on a first control signal, at least a second controlling device for distributing the total energy between the N outputs by means of at least a second control signal, wherein the first controlling device is coupled to all N outputs for receiving a number M of the respective feedback output signals of the N outputs, M?N, wherein the first controlling device comprises first means for weighting the M feedback output signals and second means for providing the first control signal dependent on the weighted M feedback output signals.

Abstract: Circuits and methods to achieve a voltage-to-current converter having low noise and a high linearity are disclosed. In a preferred embodiment the converter has been used as a Gm integrator. The core of the invention is an operational transconductance amplifier (OTA) having additional DC current sources allowing a common mode voltage shift. The feedback currents and output currents are decoupled by means of current mirrors. The feedback currents are higher than the output currents thus allowing lower integration resistor size. A common mode decoupling of input and output has been achieved by current mirrors.

Abstract: Circuits and methods to achieve a voltage-to-current converter having low noise and a high linearity are disclosed. In a preferred embodiment the converter has been used as a Gm integrator. The core of the invention is an operational transconductance amplifier (OTA) having additional DC current sources allowing a common mode voltage shift. The feedback currents and output currents are decoupled by means of current mirrors. The feedback currents are higher than the output currents thus allowing lower integration resistor size. A common mode decoupling of input and output has been achieved by current mirrors.

Abstract: Circuits and methods to achieve a low-noise and low offset continuous sigma-delta modulator used e.g. for battery management are disclosed. Continuous integration of input is enabled by special switching principle of three parallel integrators. Precharging of integrator output in so called pre-run mode minimizes integrator leakage and non-ideal effects by connecting a Gm in pre-run mode either to input voltage or to a reference voltage depending this Gm is being used in a following clock period. Parasitic effects due to switching at first integration capacitor are minimized by using buffer amplifiers tracking the voltage on integration capacitors.

Abstract: A new method and a circuit to improve the low voltage performance of a differential gain stage is achieved. The method comprises a monitoring stage and a differential stage. The monitoring stage comprises a differential transistor pair having first and second differential inputs, an upper current input, and a lower current output. In addition, a current source is connected to the upper current input, and a current load is connected to the lower current output. The differential stage comprises a differential transistor pair having first and second differential inputs, an upper current input, and first and second lower current outputs. In addition, a current source is connected to the upper current input, and first and second current loads are connected to the first and second lower current inputs. A current is forced through the monitoring stage current source. The current through the monitoring stage current source is mirrored in the differential stage current source.

Abstract: A new method and a circuit to improve the low voltage performance of a differential gain stage is achieved. The method comprises a monitoring stage and a differential stage. The monitoring stage comprises a differential transistor pair having first and second differential inputs, an upper current input, and a lower current output. In addition, a current source is connected to the upper current input, and a current load is connected to the lower current output. The differential stage comprises a differential transistor pair having first and second differential inputs, an upper current input, and first and second lower current outputs. In addition, a current source is connected to the upper current input, and first and second current loads are connected to the first and second lower current inputs. A current is forced through the monitoring stage current source. The current through the monitoring stage current source is mirrored in the differential stage current source.

Abstract: A circuit and method are given, to realize a high voltage comparator, which generates an output signal for follow-up processing in the low-voltage domain. The high-voltage comparison task is essentially replaced by a current comparison, implemented as a combination of a voltage to current transforming stage with a CMOS current comparator circuit, where only very few parts are working in the high voltage domain. Using the intrinsic advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only four discrete or integrated extended drain MOS components at low cost. This solution reduces the complexity of the circuit and in consequence also power consumption and manufacturing cost.

Abstract: A new floating gate programmable device cell is achieved. The device comprises, first, a negative injection transistor having drain, source, bulk, and gate. The source and bulk are coupled to ground. The drain forms an output of the cell. A positive injection transistor has drain, source, bulk, and gate. The drain, source, and bulk are coupled to a programming voltage. The gate is coupled to the negative injection transistor gate to form a floating gate node. Finally, a capacitor has a first terminal coupled to the floating gate node and a second terminal coupled to a control voltage. The states of the programming voltage and the control voltage determine negative charge injection onto the floating gate node and positive charge injection onto the floating gate node. A voltage on the floating gate node comprises a nonvolatile memory state that is detectable by the impedance of the output.

Abstract: A method to control the illumination intensity of a gas discharge lamp is achieved. The method comprises, first, converting an analog lamp illumination signal into a digital lamp illumination signal. The analog lamp illumination signal is a function of the illumination intensity of a gas discharge lamp. Second, digital target signal is subtracted from the digital lamp illumination signal to create a digital error signal. Third, a digital frequency set point is adjusted from a current value to a new value based on the digital error signal. The digital frequency set point is a high resolution digital value. Fourth, the current value and the new value are averaged by a digital delta sigma modulator to create a smoothed frequency set point. The smoothed frequency set point is a medium resolution value. Finally, an oscillating voltage signal is generated with a drive frequency based on the smoothed frequency set point. The drive frequency determines the illumination intensity of the gas discharge lamp.

Abstract: A new high voltage, high side driver circuit has been achieved. The circuit comprises, first, a top PFET having gate, drain, source, and bulk. The gate is coupled to a switching signal. The source is coupled to a high voltage. Second, a top resistor has first and second terminals. The first terminal is coupled to the high voltage. Third, a middle PFET cell comprises a middle PFET having gate, drain, source, and bulk. The source is coupled to the top PFET drain. The gate is coupled to the top resistor second terminal. A middle resistor has first and second terminals. The first terminal is coupled to the middle PFET gate. Finally, a middle means of claimping the middle PFET gate and a clamping voltage completes the middle PFET cell. Fourth, a bottom PFET cell comprises, first, a bottom PFET having gate, drain, source, and bulk. The gate is coupled to the middle resistor second terminal, the source is coupled to the middle PFET drain, and the drain forms a high side driver output.

Abstract: A new floating gate programmable device cell is achieved. The device comprises, first, a negative injection transistor having drain, source, bulk, and gate. The source and bulk are coupled to ground. The drain forms an output of the cell. A positive injection transistor has drain, source, bulk, and gate. The drain, source, and bulk are coupled to a programming voltage. The gate is coupled to the negative injection transistor gate to form a floating gate node. Finally, a capacitor has a first terminal coupled to the floating gate node and a second terminal coupled to a control voltage. The states of the programming voltage and the control voltage determine negative charge injection onto the floating gate node and positive charge injection onto the floating gate node. A voltage on the floating gate node comprises a nonvolatile memory state that is detectable by the impedance of the output.

Abstract: An apparatus and a method for controlling a converter of electronic power supply energy embodied for example as a boost converter or as a boost converter with a power factor correction (PFC) or being used as a DC to DC converter that is running in a discontinuous mode and which is using an equation to calculate the point of time of the zero current state of the storage inductor based on the ON time of the shunt switch and the voltages at the source and the load side. This method achieves a maximum power transfer by recharging of the storage inductor right after the zero current state is reached. The accuracy of the voltage measurement is increased by calibration of the source and load voltage dividers. Minimizing distortion and harmonics is achieved by a fine adjustment of the energy transfer through fine-tuning of the pulse width of the switch overcoming the limitations of discrete time steps in clocked digital systems by toggling between neighboring ON time values of the switch.

Abstract: The output driver circuit of an integrated circuit has several pairs of driver circuits and driver control circuits as well as a control device. Each pair of driver control circuit and driver circuit forms a driver stage. The driver stages are connected in series. Based on the input signal of the output driver circuit, the control device switches the signal direction through the succession of driver stages in such a way that, at the time the output driver circuit is switched either on or off, the driver stages are switched in a time delayed manner, whereby current pulses on the feeding lines and disturbance voltages induced in inductive loads are reduced.