Abstract: A method of modeling a programmable processor is particularly adapted for use in an automatic retargetable code generator and instruction set simulator. The method represents the processor as a single graph with vertices and edges. The graph includes the instruction set of the processor and includes information about the hardware of the processor. The graph is linked to tools and libraries required to program and simulate the processor.

Abstract: The present invention concerns a method of generating code for a programmable processor and comprises several steps. The first step is representing the processor as a directed bipartite graph with first and second sets of vertices and with edges, the graph comprising essentially all information about an instruction set and hardware of the processor, the first set of vertices representing storage elements in the processor, and the second set of vertices representing operations in the processor. The second step includes linking the graph to tools and libraries required for generating code for the processor. The last step is executing the required code generation phases, whereby the required information about the processor is extracted from the graph. The present invention also concerns the application of this method.