Abstract: A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional cycles of the first voltage waveform are obtained. The samples are obtained in response to a control signal indicative of a code used to produce the first voltage waveform, and the samples are combined to produce the second voltage waveform.

Abstract: To conserve power in a circuit where a high-speed signal HSIG controls combinational logic (10), while a low-speed signal LCLK drives a logic/memory circuit (12) that samples the output of the combinational logic, predictive logic state machine (14) generates a clock, P_LCLK, which has an active level preceding the active edge of LCLK by a period sufficient to allow the combinational logic to reach the desired state prior to the active edge of LCLK and, preferably, allows for possible jitter in LCLK. Responsive to P_LCLK, the signal suspend circuitry (16) either passes HSIG or gates off HSIG. Further reductions in power can be accomplished by predicting which portions of the logic/memory circuit (12) will be used, and clocking those portions.

Abstract: A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word.

Abstract: A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.

Abstract: A frequency synthesizer (500) includes a DDFS (502) and a PLL loop (526). The oscillator frequency signal (516) is used to create the DDFS clock signal (514), fCLK that acts as a system clock for the DDFS (502). With the phase/frequency state of the DDFS being adjusted based on a comparison of the DDFS system clock signal (514) with a frequency reference signal (520), fREF. The DDFS system clock signal (514) is further divided by a divider (512) to establish an update clock signal (528), fupdate. The output of the DDFS and the update clock signal (528) are compared by a phase/frequency detector (504). The output signal of the PFD (504) is preferably filtered by a loop filter (506) before using it as a tuning signal (522) for the DCO (508). The principle of bootstraping ensures that the synthesizer (500) is synchronous and every clock is derived from the same source.

Abstract: A technique of time dithering a fully digitally-controlled oscillator (DCO) tuning input employs a shift register 1306 and a multiplexer 1308 responsive to a sigma-delta modulated delay control to minimize spurious tones generated by a DCO 200. The shift register 1306 is clocked via a divided-down high-frequency reference provided by the DCO 200 output signal. The multiplexer 1308 is clocked via a frequency reference that is reclocked and synchronized to the DCO 200 output signal. The multiplexer 1308 output is thus time dithered in response to a delay control to minimize perturbations caused by switching.

Abstract: A high resistivity silicon for RF passive operation including CMOS structures with implanted CMOS wells and a buried layer under the wells formed by deep implants during well implantations.

Abstract: A frequency synthesizer architecture naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase-domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information.

Abstract: A multi-tap, digital-pulse-driven mixer advantageously avoids local oscillator (11) leakage by shifting the local oscillator frequency (FLO) out of the received frequency band. Low noise figures are advantageously realized by the use of digital pulses (51, 52) as mixer drive signals (16).

Abstract: A frequency synthesizer (500) includes a DDFS (502) and a PLL loop (526). The oscillator frequency signal (516) is used to create the DDFS clock signal (514), fCLK that acts as a system clock for the DDFS (502). With the phase/frequency state of the DDFS being adjusted based on a comparison of the DDFS system clock signal (514) with a frequency reference signal (520), fREF. The DDFS system clock signal (514) is further divided by a divider (512) to establish an update clock signal (528), fupdate. The output of the DDFS and the update clock signal (528) are compared by a phase/frequency detector (504). The output signal of the PFD (504) is preferably filtered by a loop filter (506) before using it as a tuning signal (522) for the DCO (508). The principle of bootstraping ensures that the synthesizer (500) is synchronous and every clock is derived from the same source.