Patents by Inventor Dirk Michels
Dirk Michels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8973007Abstract: According to one aspect of the present disclosure, a method and technique for adaptive lock list searching of waiting threads includes determining an average service time for a lock associated with a shared computing resource; determining an average search time for selecting a thread to next receive the lock from a plurality of threads waiting for the lock; summing the average service time and the average search time; applying a search factor to the summed average service time and average search time to obtain a target search time for searching the waiting threads for selecting the next thread for obtaining the lock; determining a quantity of waiting threads to consider for next obtaining the lock based on the target search time and the average search time, the quantity being less than a total quantity of waiting threads; and identifying the next thread to obtain the lock from the quantity.Type: GrantFiled: December 9, 2013Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20150051436Abstract: An intravascular blood pump having a drive section (11), a catheter (14) fastened to the drive section proximally and a pump section (12) fastened to the drive section distally possesses an electric motor (21) whose motor shaft (25) is mounted in the drive section (11) with two radial sliding bearings (27, 31) and an axial sliding bearing (40). During operation, purge fluid is conveyed through the bearing gap of the axial sliding bearing (40) and further through the radial sliding bearing (31) at the distal end of the drive section (11). The purge fluid is highly viscous, for example 20% glucose solution.Type: ApplicationFiled: February 14, 2013Publication date: February 19, 2015Inventors: Gerd Spanier, Frank Kirchhoff, Thorsten Siess, Dirk Michels
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Patent number: 8954974Abstract: A system and technique for adaptive lock list searching of waiting threads includes logic executable by a processor to: determine an average service time for a lock associated with a shared computing resource; determine an average search time for selecting a thread to next receive the lock from a plurality of threads waiting for the lock; sum the average service time and the average search time; apply a search factor to the summed average service time and average search time to obtain a target search time for searching the waiting threads for selecting the next thread for obtaining the lock; determine a quantity of waiting threads to consider for next obtaining the lock based on the target search time and the average search time, the quantity being less than a total quantity of waiting threads; and identify the next thread to obtain the lock from the quantity.Type: GrantFiled: November 10, 2013Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 8935700Abstract: Provided are techniques for providing a first lock, corresponding to a resource, in a memory that is global to a plurality of processor; spinning, by a first thread running on a first processor of the processors, at a low hardware-thread priority on the first lock such that the first processor does not yield processor cycles to a hypervisor; spinning, by a second thread running on a second processor, on a second lock in a memory local to the second processor such that the second processor is configured to yield processor cycles to the hypervisor; acquiring the lock and the corresponding resource by the first thread; and, in response to the acquiring of the lock by the first thread, spinning, by the second thread, at the low hardware-thread priority on the first lock rather than the second lock such that the second processor does not yield processor cycles to the hypervisor.Type: GrantFiled: December 13, 2013Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: Dirk Michel, Bret R. Olszewski, Basu Vaidyanathan
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Patent number: 8930952Abstract: Provided are techniques for providing a first lock, corresponding to a resource, in a memory that is global to a plurality of processor; spinning, by a first thread running on a first processor of the processors, at a low hardware-thread priority on the first lock such that the first processor does not yield processor cycles to a hypervisor; spinning, by a second thread running on a second processor, on a second lock in a memory local to the second processor such that the second processor is configured to yield processor cycles to the hypervisor; acquiring the lock and the corresponding resource by the first thread; and, in response to the acquiring of the lock by the first thread, spinning, by the second thread, at the low hardware-thread priority on the first lock rather than the second lock such that the second processor does not yield processor cycles to the hypervisor.Type: GrantFiled: March 21, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Dirk Michel, Bret R. Olszewski, Basu Vaidyanathan
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Patent number: 8775749Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle, while preventing direct access of the pinned and allocated pages by the user processes without use of the handles; scanning periodically hardware status bits in the inodes to determine which of the pinned and allocated pages have been recently accessed within a pre-determined period of time; requesting via a callback communication to each user process to determine which of the least-recently accessed pinned and allocated pages can be either deallocated or defragmented and compacted; and responsive to receiving one or more page indicators of pages unpinned by the user processes, compacting or deallocating one or more pages corresponding to the page indicators.Type: GrantFiled: June 26, 2013Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20140149675Abstract: An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred.Type: ApplicationFiled: December 11, 2013Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Accapadi, Grover C. Davidson, Dirk Michel, Bret R. Olszewski
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Publication number: 20140149672Abstract: An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mathew Accapadi, Grover C Davidson, II, Dirk Michel, Bret R Olszewski
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Publication number: 20140101662Abstract: Provided are techniques for providing a first lock, corresponding to a resource, in a memory that is global to a plurality of processor; spinning, by a first thread running on a first processor of the processors, at a low hardware-thread priority on the first lock such that the first processor does not yield processor cycles to a hypervisor; spinning, by a second thread running on a second processor, on a second lock in a memory local to the second processor such that the second processor is configured to yield processor cycles to the hypervisor; acquiring the lock and the corresponding resource by the first thread; and, in response to the acquiring of the lock by the first thread, spinning, by the second thread, at the low hardware-thread priority on the first lock rather than the second lock such that the second processor does not yield processor cycles to the hypervisor.Type: ApplicationFiled: December 13, 2013Publication date: April 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dirk Michel, Bret R. Olszewski, Basu Vaidyanathan
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Patent number: 8607239Abstract: Two or more processors that each provides a specified thread to access a shared resource that can only be accessed by one thread at a given time. A locking mechanism enables one of the threads to access the shared resource while other threads are retained in a waiting queue. Responsive to an additional thread that is not one of the specified threads being provided access the shared resource during an identified time period, and responsive to a first criterion an a second criterion being met, the additional thread accesses the shared resource before the other threads in the waiting queue.Type: GrantFiled: December 31, 2009Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Vaijayanthimala K. Anand, David A. Hepkin, Dirk Michel, Bret R. Olszewski
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Publication number: 20130290666Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle, while preventing direct access of the pinned and allocated pages by the user processes without use of the handles; scanning periodically hardware status bits in the inodes to determine which of the pinned and allocated pages have been recently accessed within a pre-determined period of time; requesting via a callback communication to each user process to determine which of the least-recently accessed pinned and allocated pages can be either deallocated or defragmented and compacted; and responsive to receiving one or more page indicators of pages unpinned by the user processes, compacting or deallocating one or more pages corresponding to the page indicators.Type: ApplicationFiled: June 26, 2013Publication date: October 31, 2013Applicant: IBM CORPORATIONInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20130254775Abstract: Provided are techniques for providing a first lock, corresponding to a resource, in a memory that is global to a plurality of processor; spinning, by a first thread running on a first processor of the processors, at a low hardware-thread priority on the first lock such that the first processor does not yield processor cycles to a hypervisor; spinning, by a second thread running on a second processor, on a second lock in a memory local to the second processor such that the second processor is configured to yield processor cycles to the hypervisor; acquiring the lock and the corresponding resource by the first thread; and, in response to the acquiring of the lock by the first thread, spinning, by the second thread, at the low hardware-thread priority on the first lock rather than the second lock such that the second processor does not yield processor cycles to the hypervisor.Type: ApplicationFiled: March 21, 2012Publication date: September 26, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dirk Michel, Bret R. Olszewski, Basu Vaidyanathan
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Publication number: 20130227549Abstract: Systems, methods and computer program products may provide managing utilization of one or more physical processors in a shared processor pool. A method of managing utilization of one or more physical processors in a shared processor pool may include determining a current amount of utilization of the one or more physical processors and generating an instruction message. The instruction message may be at least partially determined by the current amount of utilization. The method may further include sending the instruction message to a guest operating system, the guest operating system having a number of enabled virtual processors.Type: ApplicationFiled: February 23, 2012Publication date: August 29, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 8499138Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle. Direct access of the pinned and allocated pages by the user processes without use of the handles is prevented. Hardware status bits in the inodes are scanned to determine which pinned and allocated pages have been recently accessed and callback communication to each user process is used to determine which of the least-recently accessed pages can be deallocated, defragmented and compacted.Type: GrantFiled: June 30, 2010Date of Patent: July 30, 2013Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C Davidson, II, Dirk Michel, Bret R Olszewski
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Patent number: 8489824Abstract: A method, system, and computer usable program product for selective memory compression for multi-threaded applications are provided in the illustrative embodiments. An identification of a memory region that is shared by a plurality of threads in an application is received at a first entity in a data processing system. A request for a second entity in the data processing system to keep the memory region uncompressed when compressing at least one of a plurality of memory regions that comprise the memory region is provided from the first entity to the second entity.Type: GrantFiled: September 20, 2010Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
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Publication number: 20130179616Abstract: Interrupt-intensive and interrupt-driven processes are managed among a plurality of virtual processors, wherein each virtual processor is associated with a physical processor, wherein each physical processor may be associated with a plurality of virtual processors, and wherein each virtual processor is tasked to execute one or more of the processes, by determining which of a plurality of the processes executing among a plurality of virtual processors are being or have been driven by at least a minimum count of interrupts over a period of operational time; selecting a subset of the plurality of virtual processors to form a sequestration pool; migrating the interrupt-intensive processes on to the sequestration pool of virtual processors; and commanding by a computer a bias in delivery or routing of the interrupts to the sequestration pool of virtual processors.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
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Patent number: 8359449Abstract: A method manages memory paging operations. Responsive to a request to page out a memory page from a shared memory pool, the method identifies whether a physical space within one of a number of paging space devices has been allocated for the memory page. If physical space within the paging space device has not been allocated for the memory page, a page priority indicator for the memory page is identified. The memory page is then allocated to one of a number of memory pools within one of the number of paging space devices. The memory page is allocated one of the memory pools according to the page priority indicator of the memory page. The memory page is then written to the allocated memory pools.Type: GrantFiled: December 17, 2009Date of Patent: January 22, 2013Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Dirk Michel, Bret Ronald Olszewski
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Patent number: 8327176Abstract: Distributing a thread for running on a physical processor and enabling the physical processor to be switched into a low power snooze state when said running thread is IDLE. However, this switching into said low power state is enabled to be delayed by a delay time from an IDLE dispatch from said running thread; such delay is determined by tracking the rate of the number of said IDLE dispatches per processor clock interval and dynamically varying said delay time wherein the delay time is decreased when said rate of IDLE dispatches increases and the delay time is increased when said rate of IDLE dispatches decreases.Type: GrantFiled: March 31, 2010Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
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Patent number: 8307188Abstract: An information handling system (IHS) loads an application that may include startup code and steady state operation code. The IHS allocates one region of system memory to the startup code and another region of system memory to the steady state operation code. A programmer inserts a memory release call command at a location that marks the end of execution of the startup code. After executing the startup code, the operation system receives the memory release call command. In response to the memory release call command, the operating system releases or de-allocates the region of memory to which the IHS previously assigned to the startup code. This enables the released memory for use by code other than the startup code, such as other code pages, library pages and other code.Type: GrantFiled: November 10, 2009Date of Patent: November 6, 2012Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
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Publication number: 20120278809Abstract: The present invention provides a computer implemented method and apparatus to assign software threads to a common virtual processor of a data processing system having multiple virtual processors. A data processing system detects cooperation between a first thread and a second thread with respect to a lock associated with a resource of the data processing system. Responsive to detecting cooperation, the data processing system assigns the first thread to the common virtual processor. The data processing system moves the second thread to the common virtual processor, whereby a sleep time associated with the lock experienced by the first thread and the second thread is reduced below a sleep time experienced prior to the detecting cooperation step.Type: ApplicationFiled: July 9, 2012Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Larry B. Brenner, Dirk Michel, Bret R. Olszewski