Patents by Inventor Dirk N. Anderson
Dirk N. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6861348Abstract: A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).Type: GrantFiled: October 18, 2001Date of Patent: March 1, 2005Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
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Patent number: 6720247Abstract: A low-k dielectric layer (104) is treated with a dry H2 plasma pretreatment to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The H2 plasma pre-treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).Type: GrantFiled: October 25, 2001Date of Patent: April 13, 2004Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
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Patent number: 6559050Abstract: A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSiYNZ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via.Type: GrantFiled: October 19, 2000Date of Patent: May 6, 2003Assignee: Texas Instruments IncorporatedInventors: William R. McKee, Jiong-Ping Lu, Ming-Jang Hwang, Dirk N. Anderson, Wei Lee
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Publication number: 20020111037Abstract: A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).Type: ApplicationFiled: October 18, 2001Publication date: August 15, 2002Inventors: Brian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
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Publication number: 20020111017Abstract: A low-k dielectric layer (104) is treated with a dry H2 plasma pretreatment to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The H2 plasma pre-treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).Type: ApplicationFiled: October 25, 2001Publication date: August 15, 2002Inventors: Brian K. Kirkpatrick, Michael Morrison, Andrew J. McKerrow, Kenneth J. Newton, Dirk N. Anderson
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Patent number: 6380008Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).Type: GrantFiled: December 14, 2000Date of Patent: April 30, 2002Assignee: Texas Instruments IncorporatedInventors: Siang Ping Kwok, William F. Richardson, Dirk N. Anderson
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Patent number: 6373088Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).Type: GrantFiled: June 10, 1998Date of Patent: April 16, 2002Assignee: Texas Instruments IncorporatedInventors: Siang Ping Kwok, William F. Richardson, Dirk N. Anderson
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Publication number: 20010026004Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).Type: ApplicationFiled: June 10, 1998Publication date: October 4, 2001Inventors: SIANG PING KWOK, WILLIAM F. RICHARDSON, DIRK N. ANDERSON
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Patent number: 6245605Abstract: A method for protecting metal (112) from oxidation during various oxidation steps such as CVD SiO2 oxidation for forming an overlying oxide layer (114), smile oxidation, and sidewall (116) deposition. The gas CO2 is added to the oxidation chemistry. The CO2/H2 ratio is controlled for selective oxidation. The metal (112) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagents.Type: GrantFiled: August 5, 1999Date of Patent: June 12, 2001Assignee: Texas Instruments IncorporatedInventors: Ming Hwang, Wei-Yung Hsu, Chih-Chen Cho, Dirk N. Anderson
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Publication number: 20010001724Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).Type: ApplicationFiled: December 14, 2000Publication date: May 24, 2001Inventors: Slang Ping Kwok, William F. Richardson, Dirk N. Anderson
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Patent number: 6187656Abstract: A process for forming a W-poly gate stack (110) comprising the steps of: (1) deposition of doped polysilicon (112) on a thin dielectric layer (108) covered substrate (102), (2) deposition of WNx by a CVD-based process, (3) thermal treatment to covert WNx into thermally stable barrier, WSiNx, (114) and to remove excess nitrogen and (4) deposition of W layer (116). The stack layers are then etched to form the gate electrode (110).Type: GrantFiled: October 7, 1998Date of Patent: February 13, 2001Assignee: Texas Instruments IncorporatedInventors: Jiong Ping Lu, Ming Hwang, Dirk N. Anderson, Jorge A. Kittl, Hun-Lian Tsai
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Patent number: 6159835Abstract: An encapsulated gate structure includes a polysilicon layer, a barrier layer overlying the polysilicon layer and having opposing sidewalls, a metal layer overlying the barrier layer and having opposing sidewalls, a top dielectric layer overlying the metal layer and having opposing sidewalls, and a vertically oriented dielectric layer extending over and covering each of the opposing sidewalls of the barrier layer and the metal layer to encapsulate the barrier layer and metal layer on the polysilicon layer. The encapsulated gate and barrier layer are thus unaffected by oxidation and other similar detrimental effects of subsequent processing steps.Type: GrantFiled: April 6, 2000Date of Patent: December 12, 2000Assignee: Texas Instruments IncorporatedInventors: Mark R. Visokay, Dirk N. Anderson
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Patent number: 5796151Abstract: In an integrated circuit, gate electrode stack of which is subjected to self-alignment processes, the sheet resistance is lowered by including a tungsten layer 15. The tungsten layer 14 is protected by a sidewall material 21 of SiN.sub.x or SiO.sub.2 after an etching step which did not extend to the substrate 11. During a subsequent etching step in which the stack extends to the substrate 11, the sidewall material 31 acts as a hard mask protecting the upper portion of the stack. After the lower portion of the stack is protected by a re-oxidation layer 41, the entire stack can be processed further without deterioration of the sheet resistance of the tungsten layer 15.Type: GrantFiled: December 19, 1996Date of Patent: August 18, 1998Assignee: Texas Instruments IncorporatedInventors: Wei-Yung Hsu, Dirk N. Anderson, Robert Kraft
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Patent number: 5300447Abstract: An extremely small minimum scaled Metal-Oxide-Semiconductor, MOS, transistor is manufactured by forming a trench in a semiconductor substrate, forming a gate in the trench, and then forming source and drain regions. The source and drain regions may be diffused into the semiconductor substrate and annealed to drive the diffusions around the trench corners, thus forming the transistor channel. This improves punchthrough resistance of the transistor while yielding an extremely small gate channel. The diffusion concentration will be larger near the surface of the semiconductor substrate and smaller near the plane of the gate channel underneath the trench bottom. The trench corners have the effect of serving as a line source of dopant for diffusion under the trench such that the doping profile is the same along a radius of a cylindrical junction, thus keeping the minimum diffusion separation at the channel surface.Type: GrantFiled: September 29, 1992Date of Patent: April 5, 1994Assignee: Texas Instruments IncorporatedInventor: Dirk N. Anderson
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Patent number: 5216265Abstract: A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.Type: GrantFiled: December 18, 1991Date of Patent: June 1, 1993Assignee: Texas Instruments IncorporatedInventors: Dirk N. Anderson, William R. McKee, Cishi Chung
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Patent number: 5112762Abstract: A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.Type: GrantFiled: December 5, 1990Date of Patent: May 12, 1992Inventors: Dirk N. Anderson, William R. McKee, Gishi Chung
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Patent number: 4922320Abstract: The specification discloses a method and a device wherein circuit elements (10) are formed on the surface of a semiconductor body (12). A layer of oxide (22) is applied over the circuit element (10). An aperture (32) is opened through the oxide layer (22). The surface of oxide layer (22) is nonuniformly substantially roughened. A layer of metal (24) such as aluminum is formed over the oxide layer (22) and extends into the aperture (32) for contact with a portion of the device (10). The layer of metal (24) has increased granular structure and a roughened exterior surface to provide enhanced electromigration properties.Type: GrantFiled: February 16, 1988Date of Patent: May 1, 1990Assignee: Texas Instruments IncorporatedInventors: James M. McDavid, Dirk N. Anderson
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Patent number: 4808552Abstract: A process is disclosed for making a conductive interconnecting path formed between two conductive areas of an integrated circuit, the conductive areas separated by at least an insulating layer of silicon nitride over a layer of oxide. The interconnecting path is formed by depositing a thick insulator coating, over the conductive and non-conductive areas then forming a vertical-walled trench, with said silicon nitride acting as an etch stop, in the thick insulator between conducting areas, then filling the trench with conductive material using chemical vapor deposition, and finally removing conductive material except for that conductive material deposited in the trench.Type: GrantFiled: June 2, 1987Date of Patent: February 28, 1989Assignee: Texas Instruments IncorporatedInventor: Dirk N. Anderson
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Patent number: 4751198Abstract: Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. A thin layer of titanium or the like is deposited, extending into a contact hole, then polysilicon is deposited over the titanium coating the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create a titanium silicide layer, including conductive sidewalls or a plug. Metal contacts and interconnections then engage the direct-reacted silicide rather than relying upon step coverage.Type: GrantFiled: September 11, 1985Date of Patent: June 14, 1988Assignee: Texas Instruments IncorporatedInventor: Dirk N. Anderson
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Patent number: 4744858Abstract: The specification discloses a method and a device wherein circuit elements (10) are formed on the surface of a semiconductor body (12). A layer of oxide (22) is applied over the circuit element (10). An aperture (32) is opened through the oxide layer (22). The surface of oxide layer (22) is nonuniformly substantially roughened. A layer of metal (24) such as aluminum is formed over the oxide layer (22) and extends into the aperture (32) for contact with a portion of the device (10). The layer of metal (24) has increased granular structure and a roughened exterior surface to provide enhanced electromigration properties.Type: GrantFiled: March 11, 1985Date of Patent: May 17, 1988Assignee: Texas Instruments IncorporatedInventors: James M. McDavid, Dirk N. Anderson