Abstract: A semiconductor-on-insulator device includes a base substrate with a background doping of a first conductivity type. A field control region of a complementary second conductivity type extends from a front surface into the base substrate. A net dopant concentration in the field control region decreases along a lateral direction parallel to the front surface at a lower rate than along a vertical direction orthogonal to the front surface. An insulator layer is formed on the front surface and a semiconductor layer is formed on the insulator layer. A semiconductor element in the semiconductor layer includes a first contact region over the field control region and a second contact region in the lateral direction of decreasing net dopant concentration in the field control region.

Abstract: A semiconductor device includes a substrate, an insulator layer, and a field plate structure. The substrate has a background doping of a first conductivity type and includes a first doped region of a second conductivity type complementary to the first conductivity type. The insulator layer is formed on a main surface of the substrate. The field plate structure is formed on the insulator layer between the first doped region and an edge structure. The field plate structure has a high-resistive and/or semi-insulating connection with at least one non-floating conductive structure.

Abstract: A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.

Abstract: A lateral high voltage semiconductor device includes a semiconductor substrate with a frontside and a semiconductor element. The semiconductor element includes: a first semiconductor region of a first conductivity type formed within the semiconductor substrate; a second semiconductor region formed within the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the frontside; and an extension region adjoining the second semiconductor region. The semiconductor device is configured to control a load current between the first and second semiconductor regions. The extension region extends along the frontside of the semiconductor substrate and includes at least one mesa protruding at the frontside of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

Abstract: A semiconductor device includes a substrate layer having a floating base region of a first conductivity type. A first well of a second conductivity type and the floating base region form a first pn junction. A first conductive structure is electrically connected to the first well. A barrier region of the second conductivity type and the floating base region form an auxiliary pn junction. A second conductive structure is electrically connected to the floating base region through a rectifying structure. A pull-down structure is configured to produce a voltage drop between the barrier region and the second conductive structure, when charge carriers cross the auxiliary pn junction.

Abstract: A semiconductor device includes a semiconductor portion including a central region and a peripheral region separating the central region from a lateral chip edge. An interlayer dielectric is formed on a horizontal first main surface of the semiconductor portion. In the peripheral region, a groove extends through the interlayer dielectric. A crack arresting structure includes a first portion formed in the groove. A dielectric layer structure is formed on the interlayer dielectric and the crack arresting structure. The dielectric layer structure and the crack arresting structure are configured such that each horizontal plane intersecting the dielectric layer structure and the lateral chip edge intersects a tilted surface of the dielectric layer structure in the peripheral region.

Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

Abstract: A lateral high voltage semiconductor device includes a semiconductor substrate with a frontside and a semiconductor element. The semiconductor element includes: a first semiconductor region of a first conductivity type formed within the semiconductor substrate; a second semiconductor region formed within the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the frontside; and an extension region adjoining the second semiconductor region. The semiconductor device is configured to control a load current between the first and second semiconductor regions. The extension region extends along the frontside of the semiconductor substrate and includes at least one mesa protruding at the frontside of the semiconductor substrate.

Abstract: A lateral semiconductor device includes: a semiconductor substrate; a first insulator layer formed on the semiconductor substrate; and a semiconductor layer formed on the first insulator layer opposite to the semiconductor substrate. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, and an intermediate region interposed between the first region and the second region and defining a first lateral distance between the first region and the second region. The intermediate region has a lower doping concentration than the first region and the second region. A doping concentration of the first region at an interface to the intermediate region and a doping concentration of the second region at an interface to the intermediate region both exceed 1×1018 cm?3. The first lateral distance is at most 800 nm.

Abstract: A high voltage semiconductor device includes a substrate having a background doping of a first conductivity type. The substrate includes doped shielding regions of a complementary second conductivity type formed along a first substrate surface. An insulator layer is formed on the first substrate surface. A semiconductor layer is formed on the insulator layer opposite the substrate. A first interlayer dielectric is formed on the semiconductor layer. A first metal layer including laterally separated first field plate elements is formed on first portions of the first interlayer dielectric in a high voltage termination region. A second interlayer dielectric is formed on the first metal layer and on second portions of the first interlayer dielectric between the first field plate elements.

Abstract: A semiconductor device includes: a silicon layer having an electrically insulated backside and a thickness in a range of 10 ?m to 200 ?m between a frontside of the silicon layer and the electrically insulated backside; a high voltage region and a low voltage region formed in the silicon layer and laterally spaced apart from one another; and a first field plate structure extending from the frontside into the silicon layer. The first field plate structure includes a field plate laterally separated from the silicon layer by a dielectric material and/or a pn junction.

Abstract: A gate driver circuit includes a low side part and a high side part. The low side part outputs a first gate drive signal between a first gate output and a first reference potential. The high side part generates a high side data signal and outputs a second gate drive signal between a second gate output and a second reference potential. A p-channel junction field effect transistor structure passes the high side data signal to the low side part.

Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

Abstract: A semiconductor device includes a substrate layer having a floating base region of a first conductivity type. A first well of a second conductivity type and the floating base region form a first pn junction. A first conductive structure is electrically connected to the first well. A barrier region of the second conductivity type and the floating base region form an auxiliary pn junction. A second conductive structure is electrically connected to the floating base region through a rectifying structure. A pull-down structure is configured to produce a voltage drop between the barrier region and the second conductive structure, when charge carriers cross the auxiliary pn junction.

Abstract: A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

Abstract: An integrated circuit includes a semiconductor body with a first semiconductor layer, an insulation layer on the first semiconductor layer, and a second semiconductor layer on the insulation layer. The integrated circuit further includes a plurality of transistors each including a load path and a control node The load paths are connected in series, and the plurality of transistors are at least partially integrated in the second semiconductor layer. A voltage limiting structure is connected in parallel with the load path of one of the plurality of transistors, wherein the voltage limiting structure is integrated in the first semiconductor layer and is connected to the one of the plurality of transistors through two electrically conducting vias extending through the insulation layer.