Abstract: A circuit arrangement comprising a logic circuit to be tested and a test circuit. The logic circuit comprising logic-circuit-internal combinations configured to generate output data from input data based on a predetermined relationship. The logic circuit is configured to detect whether the relationship is satisfied and to provide an error signal if the relationship is not satisfied. The test circuit is configured to alter logic-circuit-internal combinations, to detect the error signal, and to output an alarm signal if the error signal is not detected upon alteration of the logic-circuit-internal combinations.

Abstract: A device for non-volatile storage of a status value indicating that there has been a condition, including a non-volatile storage, an energy storage for storing energy when applying a supply voltage, and a switching circuit to couple the energy storage to the non-volatile storage to write the status value thereto if the condition is present.

Abstract: A current-supply circuit includes a regulation transistor. The regulation transistor is formed to regulate, based on a first supply voltage present on a first supply-voltage feed line, a second supply voltage present on a second supply-voltage feed line. The regulation transistor provides a supply current to the second supply-voltage feed line. The voltage-supply circuit further includes an operating-point determiner, which is formed to determine, based on information that is a measure for the supply current, whether the regulation transistor is at a low operating point at which the supply current is below a determined current. The voltage-supply circuit further includes a preventer that is formed to prevent, starting from the low operating point, a rise of the supply current by at least a predetermined current amount from occurring within a predetermined period.

Abstract: A circuit arrangement comprising a logic circuit to be tested and a test circuit is provided. The logic circuit is designed to provide output data from input data, said output data being generated from the input data by logic-circuit-internal combinations, such that the output data are in a predetermined relationship with the input data. The logic circuit is designed to detect whether the relationship is fulfilled and to provide an error signal if the relationship is not fulfilled. The test circuit is designed to alter logic-circuit-internal combinations. The test circuit is designed to detect the error signal, and is furthermore designed to output an alarm signal if the error signal is not detected upon alteration of the logic-circuit-internal combinations.

Abstract: An integrated circuit arrangement including at least one circuit part which is designed to run through a functional self test and to output test results of the functional self test, and a testing unit, which is coupled to an input and an output and which is coupled to the at least one circuit part via testing lines. The testing unit is designed to start the functional self test when a starting signal for the functional self test is applied to the input, to evaluate test results that are present to determine whether they have a predefined relationship with predefined values, and to output data indicating the test result at the output. The testing unit is also designed to start the functional self test by internal circuit means and to evaluate the test results present.

Abstract: An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining the instruction. In the case of the presence of LCALL or FCALL, a stack memory is filled, while the stack is emptied in the case of the presence of a re-jump instruction. At every re-jump, a predetermined amount of re-jump information is taken from stack and supplied to a means for decoding, which is formed to access the stack again in the case where the predetermined amount of re-jump information indicates a change of the physical memory window, to finally supply the correct address for the next instruction in the instruction sequence to the means for reading in.

Abstract: A current-supply circuit includes a regulation transistor. The regulation transistor is formed to regulate, based on a first supply voltage present on a first supply-voltage feed line, a second supply voltage present on a second supply-voltage feed line. The regulation transistor provides a supply current to the second supply-voltage feed line. The voltage-supply circuit further includes an operating-point determiner, which is formed to determine, based on information that is a measure for the supply current, whether the regulation transistor is at a low operating point at which the supply current is below a determined current. The voltage-supply circuit further includes a preventer that is formed to prevent, starting from the low operating point, a rise of the supply current by at least a predetermined current amount from occurring within a predetermined period.

Abstract: A device for non-volatile storage of a status value indicating that there has been a condition, including a non-volatile storage, an energy storage for storing energy when applying a supply voltage, and a switching circuit to couple the energy storage to the non-volatile storage to write the status value thereto if the condition is present.

Abstract: An integrated circuit arrangement including at least one circuit part which is designed to run through a functional self test and to output test results of the functional self test, and a testing unit, which is coupled to an input and an output and which is coupled to the at least one circuit part via testing lines. The testing unit is designed to start the functional self test when a starting signal for the functional self test is applied to the input, to evaluate test results that are present to determine whether they have a predefined relationship with predefined values, and to output data indicating the test result at the output. The testing unit is also designed to start the functional self test by internal circuit means and to evaluate the test results present.

Abstract: The present invention is based on the finding that free CPU operation code identifiers of a CPU or CPU operation code identifiers useable for any reason can be used to control supporting means upstream of the CPU, which is able to form, responsive to these operation code identifiers, a new, for example, physical address in relation to a second memory area having a second memory which is larger than the, for example, logic memory size addressable by the CPU. By means of the special operation code identifiers, it is thus possible in the course of an executable machine code to address the supporting means which monitors the data traffic via which the operation codes to be processed or the operation code identifiers are provided to the CPU, from the memory to the CPU, and which can take measures in relation to the new formed address when certain special operation code identifiers occur.

Abstract: An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining the instruction. In the case of the presence of LCALL or FCALL, a stack memory is filled, while the stack is emptied in the case of the presence of a re-jump instruction. At every re-jump, a predetermined amount of re-jump information is taken from stack and supplied to a means for decoding, which is formed to access the stack again in the case where the predetermined amount of re-jump information indicates a change of the physical memory window, to finally supply the correct address for the next instruction in the instruction sequence to the means for reading in.

Abstract: The present invention is based on the finding that free CPU operation code identifiers of a CPU or CPU operation code identifiers useable for any reason can be used to control supporting means upstream of the CPU, which is able to form, responsive to these operation code identifiers, a new, for example, physical address in relation to a second memory area having a second memory which is larger than the, for example, logic memory size addressable by the CPU. By means of the special operation code identifiers, it is thus possible in the course of an executable machine code to address the supporting means which monitors the data traffic via which the operation codes to be processed or the operation code identifiers are provided to the CPU, from the memory to the CPU, and which can take measures in relation to the new formed address when certain special operation code identifiers occur.