Patents by Inventor Dirk Reese
Dirk Reese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10073989Abstract: Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.Type: GrantFiled: May 8, 2017Date of Patent: September 11, 2018Assignee: Altera CorporationInventors: Bruce B. Pedersen, Dirk A. Reese
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Publication number: 20180121682Abstract: Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.Type: ApplicationFiled: May 8, 2017Publication date: May 3, 2018Inventors: Bruce B. Pedersen, Dirk A. Reese
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Patent number: 9646177Abstract: Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.Type: GrantFiled: April 29, 2011Date of Patent: May 9, 2017Assignee: Altera CorporationInventors: Bruce B. Pedersen, Dirk A. Reese
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Patent number: 9270274Abstract: Circuits, methods, and apparatus that provide for protection of configuration bitstreams from theft. One exemplary embodiment receives a scrambled configuration bitstream with an integrated circuit. The scrambled configuration bitstream is descrambled using a plurality of multiplexers under control of a security key. A configuration bitstream is received in portions. One specific embodiment uses a key stored in memory to control a bank of multiplexers that descramble each of the received portions of the configuration bitstream. Other embodiments store longer keys, and use portions of the keys to descramble one or more portions of their respective configuration bitstreams. The outputs of the multiplexers are then stored in configuration memory cells.Type: GrantFiled: January 6, 2014Date of Patent: February 23, 2016Assignee: Altera CorporationInventors: Dirk Reese, Thomas H. White
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Patent number: 9152822Abstract: Configuration data for a programmable integrated circuit device is at least partially encrypted according to at least one encryption scheme. A plurality of key stores store a plurality of decryption keys for the at least one encryption scheme. Control circuitry identifies a required key from the at least partially encrypted configuration data and generates a key selection signal. Key selection circuitry responsive to the key selection signal reads the plurality of key stores and provides the required key to the control circuitry. The control circuitry may include decryption circuitry that decrypts the at least partially encrypted configuration data using the required key. In some embodiments, different portions of the configuration data, which may represent separate partial reconfigurations of the device, require different decryption keys. Keys may be generated from combinations of the contents of the key stores.Type: GrantFiled: November 27, 2013Date of Patent: October 6, 2015Assignee: Altera CorporationInventors: Dirk A. Reese, JuJu Joyce
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Patent number: 9111121Abstract: A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may be implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD.Type: GrantFiled: June 7, 2013Date of Patent: August 18, 2015Assignee: Altera CorporationInventors: Bruce B. Pedersen, Dirk A. Reese, Juju Joyce
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Patent number: 8797061Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame.Type: GrantFiled: May 25, 2012Date of Patent: August 5, 2014Assignee: Altera CorporationInventors: Balaji Margabandu, Dirk A. Reese, Leo Min Maung, Ninh D. Ngo
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Publication number: 20140089677Abstract: Configuration data for a programmable integrated circuit device is at least partially encrypted according to at least one encryption scheme. A plurality of key stores store a plurality of decryption keys for the at least one encryption scheme. Control circuitry identifies a required key from the at least partially encrypted configuration data and generates a key selection signal. Key selection circuitry responsive to the key selection signal reads the plurality of key stores and provides the required key to the control circuitry. The control circuitry may include decryption circuitry that decrypts the at least partially encrypted configuration data using the required key. In some embodiments, different portions of the configuration data, which may represent separate partial reconfigurations of the device, require different decryption keys. Keys may be generated from combinations of the contents of the key stores.Type: ApplicationFiled: November 27, 2013Publication date: March 27, 2014Applicant: Altera CorporationInventors: Dirk A. Reese, JuJu Joyce
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Patent number: 8650409Abstract: Circuits, methods, and apparatus that provide for protection of configuration bitstreams from theft. One exemplary embodiment receives a scrambled configuration bitstream with an integrated circuit. The scrambled configuration bitstream is descrambled using a plurality of multiplexers under control of a security key. A configuration bitstream is received in portions. One specific embodiment uses a key stored in memory to control a bank of multiplexers that descramble each of the received portions of the configuration bitstream. Other embodiments store longer keys, and use portions of the keys to descramble one or more portions of their respective configuration bitstreams. The outputs of the multiplexers are then stored in configuration memory cells.Type: GrantFiled: September 15, 2004Date of Patent: February 11, 2014Assignee: Altera CorporationInventors: Dirk Reese, Thomas H. White
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Patent number: 8627105Abstract: Configuration data for a programmable integrated circuit device is at least partially encrypted according to at least one encryption scheme. A plurality of key stores store a plurality of decryption keys for the at least one encryption scheme. Control circuitry identifies a required key from the at least partially encrypted configuration data and generates a key selection signal. Key selection circuitry responsive to the key selection signal reads the plurality of key stores and provides the required key to the control circuitry. The control circuitry may include decryption circuitry that decrypts the at least partially encrypted configuration data using the required key. In some embodiments, different portions of the configuration data, which may represent separate partial reconfigurations of the device, require different decryption keys. Keys may be generated from combinations of the contents of the key stores.Type: GrantFiled: April 29, 2011Date of Patent: January 7, 2014Assignee: Altera CorporationInventors: Dirk A. Reese, JuJu Joyce
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Patent number: 8605401Abstract: Systems and methods are disclosed for securing a programmable integrated circuit device against an over-voltage attack. Generally, programmable devices, such as FPGAs, contain volatile memory registers that may store sensitive information. To prevent tampering and/or reverse engineering of such a programmable device, an over-voltage detection circuit may be employed to disable the device and/or erase the sensitive information stored on the device when an over-voltage attack is suspected. In particular, once the over-voltage detection circuit detects that the voltage applied to the programmable device exceeds a trigger voltage, it may cause logic circuitry to erase the sensitive information stored on the device. Desirably, the over-voltage detection circuit includes components arranged in such a way as to render current consumption negligible when the voltage applied to the programmable device, e.g., by a battery, remains below the trigger voltage.Type: GrantFiled: April 29, 2011Date of Patent: December 10, 2013Assignee: Altera CorporationInventors: Bruce B. Pedersen, Dirk A. Reese
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Patent number: 8581617Abstract: Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased.Type: GrantFiled: April 29, 2011Date of Patent: November 12, 2013Assignee: Altera CorporationInventors: Dirk A. Reese, Bruce B. Pedersen
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Publication number: 20130271178Abstract: A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may he implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD.Type: ApplicationFiled: June 7, 2013Publication date: October 17, 2013Inventors: Bruce B. Pedersen, Dirk A. Reese, Juju Joyce
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Publication number: 20130162290Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame.Type: ApplicationFiled: May 25, 2012Publication date: June 27, 2013Inventors: Balaji Margabandu, Dirk A. Reese, Leo Min Maung, Ninh D. Ngo
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Patent number: 8461863Abstract: A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may be implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD.Type: GrantFiled: April 29, 2011Date of Patent: June 11, 2013Assignee: Altera CorporationInventors: Bruce B. Pedersen, Dirk A. Reese, Juju Joyce
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Patent number: 8327154Abstract: A method to configure a programmable device is disclosed. The method includes receiving a scrambled configuration data at the programmable device. A bit sequence of a device tag that is stored in the programmable device is verified by determining whether the bit sequence of the device tag stored in the programmable device matches a bit sequence of a device tag within the scrambled configuration data. If the bit sequences match, the scrambled configuration data is transferred to a data re-formatter for descrambling. The descrambled configuration data is then transferred to a configuration memory of the programmable device. Circuitry that enables the method is also disclosed.Type: GrantFiled: April 29, 2011Date of Patent: December 4, 2012Assignee: Altera CorporationInventors: Dirk A. Reese, Paul B. Ekas
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Publication number: 20120275077Abstract: Systems and methods are disclosed for securing a programmable integrated circuit device against an over-voltage attack. Generally, programmable devices, such as FPGAs, contain volatile memory registers that may store sensitive information. To prevent tampering and/or reverse engineering of such a programmable device, an over-voltage detection circuit may be employed to disable the device and/or erase the sensitive information stored on the device when an over-voltage attack is suspected. In particular, once the over-voltage detection circuit detects that the voltage applied to the programmable device exceeds a trigger voltage, it may cause logic circuitry to erase the sensitive information stored on the device. Desirably, the over-voltage detection circuit includes components arranged in such a way as to render current consumption negligible when the voltage applied to the programmable device, e.g., by a battery, remains below the trigger voltage.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: ALTERA CORPORATIONInventors: Bruce B. Pedersen, Dirk A. Reese
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Publication number: 20120278632Abstract: Configuration data for a programmable integrated circuit device is at least partially encrypted according to at least one encryption scheme. A plurality of key stores store a plurality of decryption keys for the at least one encryption scheme. Control circuitry identifies a required key from the at least partially encrypted configuration data and generates a key selection signal. Key selection circuitry responsive to the key selection signal reads the plurality of key stores and provides the required key to the control circuitry. The control circuitry may include decryption circuitry that decrypts the at least partially encrypted configuration data using the required key. In some embodiments, different portions of the configuration data, which may represent separate partial reconfigurations of the device, require different decryption keys. Keys may be generated from combinations of the contents of the key stores.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: ALTERA CORPORATIONInventors: Dirk A. Reese, JuJu Joyce
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Publication number: 20120274351Abstract: A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may be implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: Altera CorporationInventors: Bruce B. Pedersen, Dirk A. Reese, Juju Joyce
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Publication number: 20120274350Abstract: Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: ALTERA CORPORATIONInventors: Dirk A. Reese, Bruce B. Pedersen