Patents by Inventor Dirk Scheideler
Dirk Scheideler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9508407Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.Type: GrantFiled: May 9, 2014Date of Patent: November 29, 2016Assignee: Micron Technology, Inc.Inventors: Maksim Kuzmenka, Dirk Scheideler, Kai Schiller
-
Publication number: 20140247681Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.Type: ApplicationFiled: May 9, 2014Publication date: September 4, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Maksim KUZMENKA, Dirk SCHEIDELER, Kai SCHILLER
-
Patent number: 8724360Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.Type: GrantFiled: December 15, 2011Date of Patent: May 13, 2014Assignee: Micron Technology, Inc.Inventors: Maksim Kuzmenka, Dirk Scheideler, Kai Schiller
-
Publication number: 20130155752Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. For example, the effective resistance on the power supply wires can be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. Further, these non-active bus wires can reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving the performance of the chip.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Applicant: Elpida Memory, Inc.Inventors: Maksim Kuzmenka, Dirk Scheideler, Kai Schiller
-
Patent number: 8271827Abstract: A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.Type: GrantFiled: December 10, 2007Date of Patent: September 18, 2012Assignee: QimondaInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 8144755Abstract: The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.Type: GrantFiled: November 29, 2007Date of Patent: March 27, 2012Inventors: Michael Bruennert, Christoph Bilger, Peter Gregorius, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 8120958Abstract: The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.Type: GrantFiled: December 24, 2007Date of Patent: February 21, 2012Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 8015438Abstract: The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.Type: GrantFiled: November 29, 2007Date of Patent: September 6, 2011Assignee: Qimonda AGInventors: Michael Bruennert, Christoph Bilger, Peter Gregorius, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 7936201Abstract: An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.Type: GrantFiled: December 22, 2006Date of Patent: May 3, 2011Assignee: Qimonda AGInventors: Edoardo Prete, Hans-Peter Trost, Anthony Sanders, Dirk Scheideler, Georg Braun, Steve Wood, Richard Johannes Luyken
-
Patent number: 7928525Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.Type: GrantFiled: April 25, 2008Date of Patent: April 19, 2011Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 7920433Abstract: Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.Type: GrantFiled: January 9, 2008Date of Patent: April 5, 2011Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 7902876Abstract: In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data1, data2), at least one clock signal input (Clock), at least one control signal input (Cnt_del1, Cnt_del2) and a data signal output (Data_out). According to the invention, the integrated circuit is configured to provide a digital data signal having a variable symbol duration at its output (Data_out), the symbol duration being controllable by means of the control signal (Cnt_del1, Cnt_del2). A further embodiment of the invention relates to a method for generating a digital data signal having a variable symbol duration in which an output signal is generated by at least one first data signal, at least one first clock signal and at least one control signal. For this purpose, at least one second clock signal is generated from the first clock signal, the second clock signal having a variable delay and the delay being set depending on the value of the at least one control signal.Type: GrantFiled: March 29, 2008Date of Patent: March 8, 2011Assignee: Qimonda AGInventors: Dirk Scheideler, Otto Schumacher, Karthik Gopalakrishnan
-
Publication number: 20110034045Abstract: Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device.Type: ApplicationFiled: August 6, 2009Publication date: February 10, 2011Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 7782927Abstract: An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.Type: GrantFiled: November 18, 2004Date of Patent: August 24, 2010Assignee: Lantiq Deutschland GmbHInventors: Philipp Börker, Bruno Celli-Urbani, Dirk Friebe, David Müller, Edoardo Prete, Volkmar Rebmann, Anthony Sanders, Dirk Scheideler
-
Patent number: 7721130Abstract: An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.Type: GrantFiled: November 27, 2006Date of Patent: May 18, 2010Assignee: Qimonda AGInventors: Edoardo Prete, Hans-Peter Trost, Anthony Sanders, Dirk Scheideler, Georg Braun, Steve Wood, Richard Johannes Luyken
-
Publication number: 20090287957Abstract: A memory control unit for controlling a memory module comprising a plurality of memory cells, said memory control unit comprising means for detecting failure of at least one memory cell, means for deactivating said at least one defective memory cell, means for assigning the address of said at least one defective memory cell to at least one replacement memory cell, first tracking means for tracking the remaining replacement memory cells and masking means to hide the address of a defective memory cell to prevent further usage of this address instead of assigning said address to a replacement memory cell.Type: ApplicationFiled: May 16, 2008Publication date: November 19, 2009Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler
-
Publication number: 20090267678Abstract: An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed.Type: ApplicationFiled: April 25, 2008Publication date: October 29, 2009Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Publication number: 20090267084Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.Type: ApplicationFiled: April 25, 2008Publication date: October 29, 2009Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Publication number: 20090243684Abstract: In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data1, data2), at least one clock signal input (Clock), at least one control signal input (Cnt_del1, Cnt_del2) and a data signal output (Data_out). According to the invention, the integrated circuit is configured to provide a digital data signal having a variable symbol duration at its output (Data_out), the symbol duration being controllable by means of the control signal (Cnt_del1, Cnt_del2). A further embodiment of the invention relates to a method for generating a digital data signal having a variable symbol duration in which an output signal is generated by at least one first data signal, at least one first clock signal and at least one control signal. For this purpose, at least one second clock signal is generated from the first clock signal, the second clock signal having a variable delay and the delay being set depending on the value of the at least one control signal.Type: ApplicationFiled: March 29, 2008Publication date: October 1, 2009Inventors: Dirk Scheideler, Otto Schumacher, Karthik Gopalakrishnan
-
Publication number: 20090190432Abstract: A DRAM chip with a data I/O-interface of an access width equal to a page size.Type: ApplicationFiled: January 28, 2008Publication date: July 30, 2009Inventors: Christoph BILGER, Peter GREGORIUS, Michael BRUENNERT, Maurizio SKERJI, Wolfgang WALTHES, Johannes STECKER, Hermann RUCKERBAUER, Dirk SCHEIDELER, Roland BARTH