Abstract: Identically structured processor boards operating in lockstep mode are frequently used for redundant systems. The deterministic behavior of all components comprised in the board, i.e. CPUS, chip sets, main memory, etc. is the basic condition for implementing a lockstep system, deterministic behavior meaning that said components simultaneously supply identical results if the components receive identical stimuli at the same time and if no error occurs. Deterministic behavior also requires the use of clocked interfaces. In many cases, asynchronous interfaces cause a certain temporal fuzziness in the system, preventing the overall behavior of the system from remaining synchronous. In order to nevertheless operate in lockstep mode, the invention relates to a method for synchronizing external events which are fed to and influence a component.

Abstract: A module for inserting into a device with a rear panel comprising a crossed pair of electric lines with a first line and a second line is provided. The module can be connected to the lines of the crossed pair of electric lines by means of a respective plug-in connection. According to the invention, the module comprises a device that compensates for the crossing of the pair of electric lines in the rear panel.

Abstract: The invention relates to a module for inserting into a device with a rear panel comprising a crossed pair of electric lines with a first line and a second line. The module can be connected to the lines of said crossed pair of electric lines by means of a respective plug-in connection. According to the invention, the module comprises a device that compensates for the crossing of the pair of electric lines in the rear panel.

Abstract: A method implemented in hardware for synchronization of identical or different redundant processing units which process identical instruction sequences and are synchronously or asynchronously clocked. In the method, transactions that are external to the processing unit are used by modules assigned to the processing unit for synchronization of the processing unit in that the processing unit is delayed, in each case, by the assigned modules until the instruction execution of the processing units has reached the current transaction.

Abstract: An electronic apparatus having a first assembly and a second assembly, which is identical to the first assembly; a bidirectional line, which connects the first and second assemblies to one another and is coupled to a voltage source; a first and a second test data providing device respectively assigned to an assembly; a first and a second line level fixing device, which are respectively assigned to an assembly, connected to the line via an interface and designed in such a way that, in response to a signal generated by the test data providing device, the line is connected to ground or isolated therefrom; a first and a second line level detecting device, which are respectively assigned to an assembly and connected to the line via the interface; and a first and a second evaluation device, which are respectively assigned to an assembly and designed in such a way that lack of correspondence between the signals of the first and second test data providing devices is detected.

Abstract: A rational frequency divider for generating an integer frequency from a rational frequency, wherein the rational frequency divider contains a memory for storing first and second divider constants, a selection device for selecting one of the stored divider constants, a first counter which counts in synchronism with the oscillations of the rational frequency, a comparison device which compares the value of the first counter with the selected divider constant, a second counter which is coupled to the selection device and the comparison device and counts a number of predetermined time intervals; and a pulse generating device for corming the integer frequency by generating a pulse in response to a signal of the comparison device.

Abstract: A method wherein an activated control signal is transmitted between two assemblies, which are driven asynchronously relative to one another, as a code signal which is switched between different conditions with a prescribed rate. In the receiving unit, the code signal is classified as an activated control signal only if an expected number of changes of condition are registered during a prescribed time period. There is thus a high degree of security against a misinterpretation of the control signal.

Abstract: In a method and circuit arrangement for level monitoring, a received or, respectively, absent data signal should be reliably recognized by the level monitoring equipment even given great fluctuations (.gtoreq.40 dB). To this end, a reference value is first calculated and stored. The reference value is then compared to samples of the received signal. The comparison result is summed and it is used to effect the output of a control signal.