Abstract: The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA?; AA?;) are provided. said sub-structures (STI; AA; AA?; AA?,) having a first sub-structure (AA?) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA?). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step.

Abstract: The invention relates to a method for producing a memory component comprising a memory location (104) having memory cells and first control electrode strips (162) for controlling the individual memory cells, and a peripheral area (106) having peripheral elements and second control electrode strips (164) for controlling said peripheral elements. The inventive method enables the expansion of the second control electrode strips (164) in the peripheral area (106) to be approximately randomly adjusted to minimum line widths, without influencing or changing the expansion of the first control electrode strips (162) in the memory location (104).

Abstract: On a substrate, first and second electrical connecting elements of an integrated circuit are disposed next to one another along a first direction. The first electrical connecting element is at a first distance from the second electrical connecting element. First and interconnects are disposed on the substrate, the first interconnect being connected to the first electrical connecting element and the second interconnect being connected to the second electrical connecting element. Third and fourth electrical connecting elements are disposed on the substrate and the first and second interconnects are disposed between the third and fourth electrical connecting elements and therebetween are at a second distance from one another, the second distance being smaller than the first distance.

Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

Abstract: An antifuse (e.g., 130) is formed in an integrated circuit through the use of a block mask (e.g., photoresist 120) during in situ antifuse dielectric formation. Generally, the mask allows self-aligned oxidation of an oxidizable metal (e.g., aluminum 104) to form the antifuse dielectric (e.g., aluminum oxide 124), while preventing oxidation of non-programmable or fixed connections (e.g., conductive stack 128). The number of mask, deposition, or etching steps may be reduced relative to prior art methods. In addition, a fixed connection may be formed during the formation of and at the same level as the antifuse link.

Abstract: A method for forming a semiconductor integrated circuit having a fuse and an active device. A dielectric layer is formed over the fuse and over a contract region of the active device. Via holes are formed through selected regions of the dielectric layer exposing underlying portions of the fuse and underlying portions of a contact region of the active device. An electrically conductive material is deposited over the dielectric layer and through the via holes onto exposed portions of the fuse and the contact region. Portions of the electrically conductive material deposited onto the fuse are selectively removed while leaving portions of the electrically conductive material deposited onto the contact region of the active device. A fill material is disposed in the one of the fuse, a bottom portion of such filling material being spaced from the fuse.

Abstract: A process for forming a DRAM in a silicon chip that includes N-MOSFETs of the memory cells in its central area and C-MOSFETs of the support circuitry in the peripheral area. By the inclusion of a masking oxide layer over the peripheral area during the formation of the memory cells, there are formed N-MOSFETs that use N-doped polycide gates and P-MOSFETs that use P-doped polycide gates. The sources and drains include self-aligned silicide contacts.

Abstract: A method for depositing an SiO.sub.2 layer, which acts as an inter-metal dielectric (IMD), is provided. The method includes the steps of applying to the topography an organodisiloxane which is dissolved in an organic solvent, the organodisiloxane is then polymerized, and the polymer formed is decomposed, the polymer changing in the process to become an SiO.sub.2 -rich layer. The method of the present invention results in SiO.sub.2 layers which achieve an excellent local and global degree of planarization and have a distinctly lower dielectric constant than SiO.sub.2 layers prepared using conventional methods.