Patents by Inventor Dirk Tobben

Dirk Tobben has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7030017
    Abstract: The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA?; AA?;) are provided. said sub-structures (STI; AA; AA?; AA?,) having a first sub-structure (AA?) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA?). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: April 18, 2006
    Assignee: Infineon Technologies AG
    Inventors: Mark Hollatz, Klaus-Dieter Morhard, Alexander Trüby, Dirk Többen
  • Patent number: 7012003
    Abstract: The invention relates to a method for producing a memory component comprising a memory location (104) having memory cells and first control electrode strips (162) for controlling the individual memory cells, and a peripheral area (106) having peripheral elements and second control electrode strips (164) for controlling said peripheral elements. The inventive method enables the expansion of the second control electrode strips (164) in the peripheral area (106) to be approximately randomly adjusted to minimum line widths, without influencing or changing the expansion of the first control electrode strips (162) in the memory location (104).
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: March 14, 2006
    Assignee: Infineon Technologies AG
    Inventor: Dirk Többen
  • Publication number: 20050020009
    Abstract: The invention relates to a method for producing a memory component comprising a memory location (104) having memory cells and first control electrode strips (162) for controlling the individual memory cells, and a peripheral area (106) having peripheral elements and second control electrode strips (164) for controlling said peripheral elements. The inventive method enables the expansion of the second control electrode strips (164) in the peripheral area (106) to be approximately randomly adjusted to minimum line widths, without influencing or changing the expansion of the first control electrode strips (162) in the memory location (104).
    Type: Application
    Filed: June 13, 2002
    Publication date: January 27, 2005
    Inventor: Dirk Tobben
  • Patent number: 6803612
    Abstract: On a substrate, first and second electrical connecting elements of an integrated circuit are disposed next to one another along a first direction. The first electrical connecting element is at a first distance from the second electrical connecting element. First and interconnects are disposed on the substrate, the first interconnect being connected to the first electrical connecting element and the second interconnect being connected to the second electrical connecting element. Third and fourth electrical connecting elements are disposed on the substrate and the first and second interconnects are disposed between the third and fourth electrical connecting elements and therebetween are at a second distance from one another, the second distance being smaller than the first distance.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: October 12, 2004
    Assignee: Infineon Technologies AG
    Inventors: Matthias Uwe Lehr, Jens Möckel, Dirk Többen
  • Patent number: 6765248
    Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: July 20, 2004
    Assignee: Infineon Technologies AG
    Inventors: Dirk Többen, Thomas Schuster
  • Publication number: 20040127040
    Abstract: The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step.
    Type: Application
    Filed: October 23, 2003
    Publication date: July 1, 2004
    Inventors: Mark Hollatz, Klaus-Dieter Morhard, Alexander Truby, Dirk Tobben
  • Publication number: 20040057301
    Abstract: On a substrate, first and second electrical connecting elements of an integrated circuit are disposed next to one another along a first direction. The first electrical connecting element is at a first distance from the second electrical connecting element. First and interconnects are disposed on the substrate, the first interconnect being connected to the first electrical connecting element and the second interconnect being connected to the second electrical connecting element. Third and fourth electrical connecting elements are disposed on the substrate and the first and second interconnects are disposed between the third and fourth electrical connecting elements and therebetween are at a second distance from one another, the second distance being smaller than the first distance.
    Type: Application
    Filed: September 15, 2003
    Publication date: March 25, 2004
    Inventors: Matthias Uwe Lehr, Jens Mockel, Dirk Tobben
  • Publication number: 20030098478
    Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.
    Type: Application
    Filed: November 25, 2002
    Publication date: May 29, 2003
    Inventors: Dirk Tobben, Thomas Schuster
  • Patent number: 6492282
    Abstract: A method of filling gaps between adjacent gate electrodes of a semiconductor structure. A self-planarizing material is deposited over the structure. A first portion of such material flow between the gate electrode to fill the gaps and a second portion of such material becomes deposited over tops of the gate electrodes and over the gaps to form a layer with a substantially planar surface. A phosphorous dopant is formed in the second portion of the self-planarizing material. Thus, relatively small gaps may be filled effectively with a layer having a very planar surface for subsequent photolithography. The phosphorous dopant provides gettering to remove adverse effects of alkali contaminant ions which may enter the gap filling material. The dielectric constant of the material filing the gaps, i.e., the first portion of the gap filling material, being substantially free of such contaminants, has a relatively low dielectric constant thereby reducing electrical coupling between adjacent electrodes.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: December 10, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Dirk Tobben, Peter Weigand, Matthias Ilg
  • Patent number: 6465282
    Abstract: An antifuse (e.g., 130) is formed in an integrated circuit through the use of a block mask (e.g., photoresist 120) during in situ antifuse dielectric formation. Generally, the mask allows self-aligned oxidation of an oxidizable metal (e.g., aluminum 104) to form the antifuse dielectric (e.g., aluminum oxide 124), while preventing oxidation of non-programmable or fixed connections (e.g., conductive stack 128). The number of mask, deposition, or etching steps may be reduced relative to prior art methods. In addition, a fixed connection may be formed during the formation of and at the same level as the antifuse link.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: October 15, 2002
    Assignee: Infineon Technologies AG
    Inventors: Dirk Többen, Axel Brintzinger, Stefan Weber
  • Patent number: 6426254
    Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces withIn the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisoropically wet etching the trench to expand the trench.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: July 30, 2002
    Assignee: Infineon Technologies AG
    Inventors: Stephen Kudelka, Alexander Michaelis, Dirk Tobben
  • Patent number: 6404000
    Abstract: A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: June 11, 2002
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp., Kabushiki Kaisha Toshiba
    Inventors: Rama Divakaruni, Rajarao Jammy, Byeong Y. Kim, Jack A. Mandelman, Akira Sudo, Dirk Tobben
  • Publication number: 20010016398
    Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisotropically wet etching the trench to expand the trench.
    Type: Application
    Filed: June 9, 1999
    Publication date: August 23, 2001
    Inventors: STEPHAN KUDELKA, ALEXANDER MICHAELIS, DIRK TOBBEN
  • Patent number: 6271142
    Abstract: A process for manufacturing a deep trench capacitor in a trench. The capacitor comprises a collar in an upper region of the trench and a buried plate in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: August 7, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ulrike Gruening, Carl J. Radens, Dirk Tobben
  • Patent number: 6261950
    Abstract: A method for connecting metal structures with self-aligned metal caps, in accordance with the invention, includes providing a metal structure in a first dielectric layer. The metal structure and the first dielectric layer share a substantially planar surface. A cap metal is selectively depositing on the metal structure such that the cap metal is deposited only on the metal structure. A second dielectric layer is formed over the cap metal. The second dielectric layer is opened to form a via terminating in the cap metal. A conductive material is deposited in the via to provide a contact to the metal structure through the cap metal.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: July 17, 2001
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Dirk Tobben, Jeffrey Gambino
  • Patent number: 6261937
    Abstract: A method for forming a semiconductor integrated circuit having a fuse and an active device. A dielectric layer is formed over the fuse and over a contract region of the active device. Via holes are formed through selected regions of the dielectric layer exposing underlying portions of the fuse and underlying portions of a contact region of the active device. An electrically conductive material is deposited over the dielectric layer and through the via holes onto exposed portions of the fuse and the contact region. Portions of the electrically conductive material deposited onto the fuse are selectively removed while leaving portions of the electrically conductive material deposited onto the contact region of the active device. A fill material is disposed in the one of the fuse, a bottom portion of such filling material being spaced from the fuse.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: July 17, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Dirk Többen, Stefan J. Weber, Axel Brintzinger
  • Patent number: 6245629
    Abstract: A method for forming source/drain contacts to source/drain regions of an array of transistors. The method includes providing a semiconductor body with a gate oxide layer over the surface of the semiconductor body. The gate oxide layer extends over active areas in the semiconductor body. Gate stacks are provided on the gate oxide layer in columns across the rows of active areas. A dielectric material is deposited over the surface of the provided semiconductor body. Vias are etched through the dielectric material over source/drain regions in portions of the active area between the columns of gate stacks. First portion of sidewalls of such vias are formed over portions of adjacent columns of the gate stacks and second portions of the sidewalls of such vias are formed between adjacent columns of the gate stacks. The vias expose portions of the gate oxide layer over the source/drain regions.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: June 12, 2001
    Assignee: Infineon Technologies North America Corp.
    Inventor: Dirk Tobben
  • Patent number: 6235574
    Abstract: A process for forming a DRAM in a silicon chip that includes N-MOSFETs of the memory cells in its central area and C-MOSFETs of the support circuitry in the peripheral area. By the inclusion of a masking oxide layer over the peripheral area during the formation of the memory cells, there are formed N-MOSFETs that use N-doped polycide gates and P-MOSFETs that use P-doped polycide gates. The sources and drains include self-aligned silicide contacts.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: May 22, 2001
    Assignee: Infineon North America Corp.
    Inventors: Dirk Többen, Johann Alsmeier
  • Patent number: 6184091
    Abstract: A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: February 6, 2001
    Assignee: Infineon Technologies North America Corp.
    Inventors: Ulrike Gruening, Jochen Beintner, Dirk Tobben, Gill Lee, Oswald Spindler, Zvonimir Gabric
  • Patent number: 6177698
    Abstract: A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: January 23, 2001
    Assignee: Infineon Technologies North America Corp.
    Inventors: Ulrike Gruening, Jochen Beintner, Dirk Tobben, Gill Lee, Oswald Spindler, Zvonimir Gabric