Abstract: The invention relates to a method for producing a memory component comprising a memory location (104) having memory cells and first control electrode strips (162) for controlling the individual memory cells, and a peripheral area (106) having peripheral elements and second control electrode strips (164) for controlling said peripheral elements. The inventive method enables the expansion of the second control electrode strips (164) in the peripheral area (106) to be approximately randomly adjusted to minimum line widths, without influencing or changing the expansion of the first control electrode strips (162) in the memory location (104).

Abstract: The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step.

Abstract: On a substrate, first and second electrical connecting elements of an integrated circuit are disposed next to one another along a first direction. The first electrical connecting element is at a first distance from the second electrical connecting element. First and interconnects are disposed on the substrate, the first interconnect being connected to the first electrical connecting element and the second interconnect being connected to the second electrical connecting element. Third and fourth electrical connecting elements are disposed on the substrate and the first and second interconnects are disposed between the third and fourth electrical connecting elements and therebetween are at a second distance from one another, the second distance being smaller than the first distance.

Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

Abstract: A method of filling gaps between adjacent gate electrodes of a semiconductor structure. A self-planarizing material is deposited over the structure. A first portion of such material flow between the gate electrode to fill the gaps and a second portion of such material becomes deposited over tops of the gate electrodes and over the gaps to form a layer with a substantially planar surface. A phosphorous dopant is formed in the second portion of the self-planarizing material. Thus, relatively small gaps may be filled effectively with a layer having a very planar surface for subsequent photolithography. The phosphorous dopant provides gettering to remove adverse effects of alkali contaminant ions which may enter the gap filling material. The dielectric constant of the material filing the gaps, i.e., the first portion of the gap filling material, being substantially free of such contaminants, has a relatively low dielectric constant thereby reducing electrical coupling between adjacent electrodes.

Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces withIn the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisoropically wet etching the trench to expand the trench.

Abstract: A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.

Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisotropically wet etching the trench to expand the trench.

Abstract: A process for manufacturing a deep trench capacitor in a trench. The capacitor comprises a collar in an upper region of the trench and a buried plate in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.

Abstract: A method for connecting metal structures with self-aligned metal caps, in accordance with the invention, includes providing a metal structure in a first dielectric layer. The metal structure and the first dielectric layer share a substantially planar surface. A cap metal is selectively depositing on the metal structure such that the cap metal is deposited only on the metal structure. A second dielectric layer is formed over the cap metal. The second dielectric layer is opened to form a via terminating in the cap metal. A conductive material is deposited in the via to provide a contact to the metal structure through the cap metal.

Abstract: A method for forming source/drain contacts to source/drain regions of an array of transistors. The method includes providing a semiconductor body with a gate oxide layer over the surface of the semiconductor body. The gate oxide layer extends over active areas in the semiconductor body. Gate stacks are provided on the gate oxide layer in columns across the rows of active areas. A dielectric material is deposited over the surface of the provided semiconductor body. Vias are etched through the dielectric material over source/drain regions in portions of the active area between the columns of gate stacks. First portion of sidewalls of such vias are formed over portions of adjacent columns of the gate stacks and second portions of the sidewalls of such vias are formed between adjacent columns of the gate stacks. The vias expose portions of the gate oxide layer over the source/drain regions.

Abstract: A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

Abstract: A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

Abstract: A method of forming a patterned conductive multilayer arrangement on a semiconductor substrate is provided which prevents photoresist poisoning by reactive nitrogenous substances from a silicon oxynitride layer forming a dielectric antireflective coating (DARC) for an overlying photoresist layer. The substrate has a first level conductive layer, e.g., of a metal, disposed in a region thereon, and is coated in turn with a dielectric insulation layer, e.g., of silicon dioxide, which overlies the first level conductive layer region, a dielectric antireflective coating (DARC) silicon oxynitride layer, an essentially reactive nitrogenous substance-free dielectric spacer layer, e.g., of spin-on glass (SOG), and a photoresist layer. The dielectric spacer layer prevents reactive nitrogenous substance transport therethrough from the DARC silicon oxynitride layer to the photoresist layer, thereby preventing poisoning of the photoresist layer.

Abstract: A process for the manufacture of silicon integrated circuits uses a dual damascene metallization process with an organic intermetal dielectric (14). A pattern to be etched is first etched in a hard mask (16) without exposing the underlying intermetal dielectric (14) and then transferred into the intermetal dielectric (14) on an enlarged scale.

Abstract: A multi-level integrated circuit metalization system having a composite dielectric layer comprising a layer 22 of diamond or sapphire. A plurality of patterned metalization layers is disposed over a semiconductor substrate 10. A composite dielectric layer is disposed between a pair of the metalization layers. The composite dielectric layer 22 comprises a layer of diamond or sapphire. The diamond or sapphire layer has disposed on a surface thereof one of the patterned metalization layers. A conductive via 34 passes through the composite layer. One end of the conductive via is in contact with diamond or sapphire layer. The diamond or sapphire layer conducts heat laterally along from the metalization layer disposed thereon to a heat sink provided by the conductive via. The patterned diamond or sapphire layer provides a mask during the second metalization deposition.

Abstract: A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.

Abstract: A method for manufacturing a dual damascene structure includes the use of a sacrificial stud and provides an improved defined edge on the interface between the conductive line openings and the via openings.

Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material.

Abstract: A substantially planar surface is produced from a non-conformal device layer formed over a complex topography, which includes narrow features with narrow gaps and wide features and wide gaps. A conformal layer is deposited over the non-conformal layer. The surface is then polished to expose the non-conformal layer over the wide features. An etch selective to the non-conformal layer is then used to substantially remove the non-conformal layer over the wide features. The conformal layer is then removed, exposing the non-conformal layer. The thickness of the non-conformal layer is now more uniform as compared to before. This enables the polish to produce a planar surface with reduced dishing in the wide spaces.