Abstract: The present invention provides a new and unique method and apparatus for a new data speed switching scheme for a wired data interface. The method features receiving high-speed serial data over a physical link using a first coding scheme in a receiver; receiving a transmission mode change signal transmitted with sequential information about a change in a data transmission mode of the receiver using a second coding scheme and switching the data transmission mode of the receiver in response thereto. The data transmission modes may include at least one low-power mode where no data transmission is possible and the receiver is powered down. The at least one low-power mode may include two different power down states, each having different wake-up times. The data transmission modes may also include at least one high speed mode where data transmission is possible and the receiver is on. The at least one high speed mode may include several high speed modes, each having different data transmission rates.

Abstract: The present invention provides a new and unique method and apparatus for a new data speed switching scheme for a wired data interface. The method features receiving high-speed serial data over a physical link using a first coding scheme in a receiver; receiving a transmission mode change signal transmitted with sequential information about a change in a data transmission mode of the receiver using a second coding scheme and switching the data transmission mode of the receiver in response thereto. The data transmission modes may include at least one low-power mode where no data transmission is possible and the receiver is powered down. The at least one low-power mode may include two different power down states, each having different wake-up times. The data transmission modes may also include at least one high speed mode where data transmission is possible and the receiver is on. The at least one high speed mode may include several high speed modes, each having different data transmission rates.

Abstract: Differential power analysis on an integrated circuit is made more difficult by providing a circuit configuration for generating current pulses in the supply current of the integrated circuit. These additional pulses that are generated in the supply current are synchronous with the edges of the internal clock signal of the integrated circuit. In this case, the pulse shape and also the amplitude and the time profile are similar to the pulses in the supply current which are generated by other circuit sections, for example by processors or by some other digital logic, and in digital circuits, typically correspond to a charging curve of a capacitor via a resistor. The circuit generates these additional pulses by using a delay element.

Abstract: The invention relates to an integrated digital circuit comprising a logic circuit portion which takes one of at least two different logic states in accordance with provided control signals. In order to minimize the power consumption and to enable a fast start up of the circuit resuming the previous states, it is proposed that it further comprises a non-volatile storage component. The non-volatile storage component takes one of at least two different logic states based on a non-destructive programming, and keeps a programmed logic state for a basically unlimited time and independently of a power supply until a new programming occurs, and is programmed by each change of the logic state of the logic circuit portion. The invention relates equally to a device comprising such a digital circuit and to a method of operating such a digital circuit.

Abstract: The invention relates to an integrated digital circuit comprising a logic circuit portion which takes one of at least two different logic states in accordance with provided control signals. In order to minimize the power consumption and to enable a fast start up of the circuit resuming the previous states, it is proposed that it further comprises a non-volatile storage component. The non-volatile storage component takes one of at least two different logic states based on a non-destructive programming, and keeps a programmed logic state for a basically unlimited time and independently of a power supply until a new programming occurs, and is programmed by each change of the logic state of the logic circuit portion. The invention relates equally to a device comprising such a digital circuit and to a method of operating such a digital circuit.

Abstract: The ESD protective circuit proceeds from a modified lateral pnpn “latch-up” protective structure having a highly doped n-type zone, which is arranged on the well boundary, along that section of the periphery of the well which runs between the two oppositely doped regions. The highly doped zone is formed of pads arranged with intermediate spacing along the section of the periphery of the well. The result is a low triggering voltage in conjunction with a low on resistance.

Abstract: Differential power analysis on an integrated circuit is made more difficult by providing a circuit configuration for generating current pulses in the supply current of the integrated circuit. These additional pulses that are generated in the supply current are synchronous with the edges of the internal clock signal of the integrated circuit. In this case, the pulse shape and also the amplitude and the time profile are similar to the pulses in the supply current which are generated by other circuit sections, for example by processors or by some other digital logic, and in digital circuits, typically correspond to a charging curve of a capacitor via a resistor. The circuit generates these additional pulses by using a delay element.

Abstract: The ESD protective circuit proceeds from a modified lateral pnpn “latch-up” protective structure having a highly doped n-type zone, which is arranged on the well boundary, along that section of the periphery of the well which runs between the two oppositely doped regions. The highly doped zone is formed of pads arranged with intermediate spacing along the section of the periphery of the well. The result is a low triggering voltage in conjunction with a low on resistance.