Abstract: A cathode ray tube includes a deflection unit. A coil system of the deflection unit is provided with a conductive layer, the value for fmax/&Dgr;f ranging between 0.5 and 10, &Dgr;f being the half-value width of the impedance curve around a peak frequency fmax, and fmax being greater that 1 MHz. This results in a reduction of ringing phenomena.

Abstract: In, for example a field emission display, the invention provides the possibility of combining a plurality of sub-substrates that are attached to a larger rear wall, because notably different modes of multiplexing provide a wider positioning tolerance of a sub-substrate with respect to the front plate. Moreover, the different multiplexing techniques lead to a smaller number of connections, even if no use is made of a rear wall supporting of sub-substrates. A plurality of multiplexing techniques provides the possibility of activating a substantially equally large number of pixels of different colours during parts of an image period, so that there is substantially no colour flicker.

Abstract: In, for example a field emission display, the invention provides the possibility of combining a plurality of sub-substrates that are attached to a larger rear wall, because notably different modes of multiplexing provide a wider positioning tolerance of a sub-substrate with respect to the front plate. Moreover, the different multiplexing techniques lead to a smaller number of connections, even if no use is made of a rear wall supporting sub-substrates. A plurality of multiplexing techniques provides the possibility of activating a substantially equally large number of pixels of different colors during parts of an image period, so that there is substantially no color flicker.

Abstract: By incorporating two-pole circuits (13) as switching elements in a picture display device based on field emission, the emission (and hence the picture intensity) is substantially defined by the charge of a capacitance (15) associated with a part of a pixel (8). Charge-controlled drive leads to a more accurate adjustment than the voltage-controlled drive used until now and leads to lower drive voltages, less power consumption and a longer lifetime of the phosphors used in the display device.

Abstract: A gate array circuit includes a row of consecutively arranged n-channel transistors and an adjacent row of p-channel transistors. Both rows are composed of at least three subrows with two subrows of narrow transistors and one subrow of wide transistors, of which the channel width is at least three times the width of the narrow transistors. The gate electrodes are common to the three subrows. Preferably, the wide subrow is arranged centrally between the narrow subrows. This construction affords the advantage of a very high density and a very high flexibility in designing the functions to be realized.

Abstract: A master slice semiconductor integrated circuit comprising ROM memory cells which consist of NMOS-transistors as well as PMOS-transistors. In order to increase the integration density on the master slice, the NMOS-transistors and the PMOS-transistors (memory cells) in one and the same row are controlled via one and the same word line. The circuit includes row selection means, for example, an exclusive-OR circuit for each row, for selecting either a single row of NMOS cells or a single row of PMOS cells.