Abstract: The present invention relates to a battery charge circuit (100) in a charge-and-play mode capable to reliably determine the completion of a battery charging operation has been described. Such a determination takes into account the behavior of the battery charge circuit (100) with respect to the temperature, the activity of the circuitry (30) and the source current limitation. Thus, a distinction can be made between a decrease of the battery charge current ICHG below the end-of-charge current level caused by the full-charge state of the battery (20) and by the activation of temperature and current regulation circuits. Furthermore, the battery charge circuit (100) is also configured such that it can be warned both that the activity of the circuitry (30) is to be limited and, by a timer (800) measuring the time interval during which the battery charge current ICHG has been reduced to zero, that the battery (20) is being discharged.

Abstract: A switched-mode power supply comprises storage means (8) for the storage of state information relating to switching times of switching means of the power supply, which state information corresponds to a load level of the load (3). The power supply further comprises detection means (9) responsive to a change in the load level of the load (3) to supply a selection signal (10) to the storage means (8) for the selection of the appropriate state information.

Abstract: A current integrator for generating an output voltage (Vo) in response to an input current (Ii) to be integrated. The input current is applied to an integration capacitor via a current-current converter. This enables one end of the integration capacitor to be connected to a fixed voltage and to be implemented by means of a MOS transistor which occupies a comparatively small area. A further area reduction is possible by making the current gain (K) of the current-current converter smaller than 1.

Abstract: A current memory cell for sampling a current (I) at a current terminal (5) during a sample interval and for applying the current (I) to the current terminal (5) during a hold interval. A first switch (S1) connects a PMOS transistor (P1) as a diode during the sample interval and as a current source during the hold interval. During the sample interval the current in the current terminal (5) is mirrored to the PMOS transistor (P1). During the hold interval the current of the PMOS transistor is mirrored to the current terminal. The mirroring is effected by means of two NMOS transistors (N1, N2) and one reversing switch (S2), which reverses the input and output of the current mirror circuit between the sample intervals and the hold intervals. The current mirror circuit (N1, N2) and the PMOS current source (P1) collectively behave as a current sink which is insensitive to the substrate voltages which are caused by the body effect.

Abstract: Dynamic accurate current divider which comprises current memory circuits (M2-C1-S3, M3-C2-S4) by means of which an input current (Iin) to be split up is divided into two almost equally large output currents (Iout1, Iout2). Under the control of a clock generator (9) having two-phase switching cycles, any inequalities in the output currents are equalized by means of the current memory circuits in a number of cycles of the clock generator.

Abstract: A signal source arrangement includes a group of signal sources calibrated so that each signal source produces an identical unit signal. The unit signals are combined to form the output signal. Each signal source also produces a similar undesirable spurious signal caused by the calibration procedure. The combination sequence or the calibration sequence is arranged so as to minimize the undesirable effect of the resulting spurious signals in the combined output signal.

Abstract: A current source arrangement in which N configurations of N+1 transistor configurations (2.1 to 2.N+1) comprising control transistors (T1 to T N+1) and control inputs (3.1 to 3.N+1) are connected to N outputs (1, 2, . . . N) by means of a switching network (7) in accordance with a cyclic pattern N. The remaining configuration is connected to a correction circuit (5) which includes a reference-current-source (6) for adjusting the control voltage of the control transistor via the control input of the relevant transistor configuration, in such a way that the output current of the relevant configuration becomes equal to that of the reference-current-source.

Abstract: A digital-to-analog converter which comprisesan input terminal (1) for receiving a digital input signal,an output terminal (2) for supplying the analog output signal,a current source circuit (3) having N current sources (I.sub.1 to I.sub.N) for generating N currents of substantially equal current intensity at N outputs (3.1 to 3N), anda combination circuit (4) having N inputs (4.1 to 4N) coupled to the N outputs of the current source circuit and an input (6) for receiving the digital input signal and an output (7).In order to convert a digital signal D which is presented to the input terminal (1) during a time interval (Ta), the time interval is sub-divided into at least two sub-intervals (T.sub.d1, T.sub.d2).

Abstract: A high accuracy current source arrangement is made up of a number of binary-weighted current sources each of which comprises a plurality of indentical transistors which are arranged regularly in a matrix of transistor elements on the surface area of an integrated circuit. The matrix of transistors is distributed over the area of the IC to provide the maximum spacing between the matrix elements (transistors) of each respective current source thereby to minimize the influence of variations in IC parameters or the like on the accuracy of the relationship of the binary-weighted currents to one another.