Abstract: The present application relates to an apparatus for verifying fragment processing related data and a method of operating thereof. The fragment shader unit is coupled to the at least one data buffer. A fragment shader unit of a graphics processing pipeline receives fragment data and records fragment processing related data in the at least one data buffer on processing one or more fragments in accordance with the received fragment data. A comparator unit coupled to the at least one data buffer compares the recorded fragment processing related data in the at least one data buffer to reference data and issues a fault indication signal in case the recorded fragment processing related data and the reference data mismatch.

Abstract: The present application relates to a system for verifying integrity of a stream of image frames including an encoder logic module and a decoder logic module. On source side, a test line insertion logic module receiving the stream is arranged upstream to the encoder logic module encoding the stream. The test line insertion logic module is configured to include one or more test lines into the image frames. A color coding is assigned to the one or more test lines. The color coding is selected from a coding scheme. On destination side, a test line detection and extraction logic module is arranged downstream to the decoder logic module receiving the encoded stream. The test line detection and extraction logic module extracts the color coding from the received image frames and verifies extracted coding data against the coding scheme. The coding data comprises at least the extracted color coding.

Abstract: A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.

Abstract: A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code.

Abstract: An electronic device includes a plurality of modules coupled to a charge storage node. A method for operating the electronic device includes starting up the electronic device and entering a demonstration mode. During the demonstration mode, a demonstration is performed for a predetermined amount of time by enabling a subset of the plurality of modules. At the expiration of the predetermined amount of time, the electronic device is shut down. If the electronic device is operating in normal operating mode, the charge level of the charge storage cell can be monitored such that when it falls below a minimum charge threshold, the electronic device is shut down. The minimum charge threshold can be based on a number of demonstrations to be performed on a remaining capacity of the charge storage cell.

Abstract: A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code.

Abstract: A memory controller includes a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data, a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information, at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme, and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.

Abstract: A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.

Abstract: The present application relates to a system for verifying integrity of a stream of image frames including an encoder logic module and a decoder logic module. On source side, a test line insertion logic module receiving the stream is arranged upstream to the encoder logic module encoding the stream. The test line insertion logic module is configured to include one or more test lines into the image frames. A color coding is assigned to the one or more test lines. The color coding is selected from a coding scheme. On destination side, a test line detection and extraction logic module is arranged downstream to the decoder logic module receiving the encoded stream. The test line detection and extraction logic module extracts the color coding from the received image frames and verifies extracted coding data against the coding scheme. The coding data comprises at least the extracted color coding.

Abstract: A data logging system for logging input data received from a data source is described. The data logging system has a data storage memory. A data input is arranged to repeatedly receive input data having a temporal input data resolution. A write controller is arranged to write newly received input data as received via the data input into the data storage memory. The writing comprises writing the newly received input data at the temporal input data resolution. The writing comprises keeping recent data at the temporal input data resolution in the data storage memory, and overwriting part of old data with newly received input data while keeping another part of the old data in the data storage memory at lower data resolution.

Abstract: An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. A write signature generation circuit generates a write signature of a second data packet. When a trigger generation circuit generates a trigger signal, a first latching circuit stores a write address as a latch write address and a second latch stores the write signature as a latch write signature. A first synchronization and comparison circuit generates a comparison signal based on the latched write address and a read address. A second synchronization and comparison circuit generates a fault signal based on the comparison signal, the latched write signature, and the read signature.

Abstract: An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. A write signature generation circuit generates a write signature of a second data packet. When a trigger generation circuit generates a trigger signal, a first latching circuit stores a write address as a latch write address and a second latch stores the write signature as a latch write signature. A first synchronization and comparison circuit generates a comparison signal based on the latched write address and a read address. A second synchronization and comparison circuit generates a fault signal based on the comparison signal, the latched write signature, and the read signature.

Abstract: The present application relates to a memory controller and a method of operating thereof. The memory controller comprises a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data; a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information; at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme; and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.

Abstract: The present invention relates to a circuit arrangement for processing a digital video stream, the circuit arrangement comprising: an input interface for receiving a digital video stream, a processing circuit which is arranged to process the digital video stream, a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising: a checksum generating circuit which is arranged to generate checksums for the frames of the processed digital video stream, a memory for storing generated checksums and an analyzing device arranged to compare a currently generated checksum to a plurality of corresponding checksums of preceding frames stored in the memory and to generate an error signal if at least one predefined amount of compared checksums are matching. The present invention also relates to a digital video system, a method for processing a digital video stream and a computer readable program product.

Abstract: A video stream decoder for decoding a multiple parallel-input video streams from multiple video cameras permits continuance of the decoding process even if one of the streams has stalled or if a start code of a currently active stream has become corrupted. A counter triggers a stream switching module to switch to a different input video stream on a round-robin or priority basis after a preset time period elapsed if no start code of a currently active stream has been detected.

Abstract: An electronic device includes a plurality of modules coupled to a charge storage node. A method for operating the electronic device includes starting up the electronic device and entering a demonstration mode. During the demonstration mode, a demonstration is performed for a predetermined amount of time by enabling a subset of the plurality of modules. At the expiration of the predetermined amount of time, the electronic device is shut down. If the electronic device is operating in normal operating mode, the charge level of the charge storage cell can be monitored such that when it falls below a minimum charge threshold, the electronic device is shut down. The minimum charge threshold can be based on a number of demonstrations to be performed on a remaining capacity of the charge storage cell.

Abstract: The present application relates to an apparatus for verifying fragment processing related data and a method of operating thereof. The fragment shader unit is coupled to the at least one data buffer. A fragment shader unit of a graphics processing pipeline receives fragment data and records fragment processing related data in the at least one data buffer on processing one or more fragments in accordance with the received fragment data. A comparator unit coupled to the at least one data buffer compares the recorded fragment processing related data in the at least one data buffer to reference data and issues a fault indication signal in case the recorded fragment processing related data and the reference data mismatch.

Abstract: An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.

Abstract: An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.

Abstract: An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.