Patents by Inventor Dirk Wollstein

Dirk Wollstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12253472
    Abstract: The present disclosure generally relates to a system and a method for detecting a defect in a specimen. More particularly, the present disclosure relates to a lithography exposure system and a method for detecting a dispensing error in a wafer The present disclosure provides a system for detecting a defect in a specimen having a lithography exposure tool including a measurement unit and a stage, the measurement unit is configured to obtain topography data of the specimen placed on the stage by illumination of a surface of the specimen with an optical signal, and a processor configured to generate a statistical data from the topography data and produce a defect notification if the statistical data is outside of a control limit.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: March 18, 2025
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Richard Paul Good, Roberto Schiwon, Matthias Ruhm, Dirk Wollstein
  • Publication number: 20240151653
    Abstract: The present disclosure generally relates to a system and a method for detecting a defect in a specimen. More particularly, the present disclosure relates to a lithography exposure system and a method for detecting a dispensing error in a wafer The present disclosure provides a system for detecting a defect in a specimen having a lithography exposure tool including a measurement unit and a stage, the measurement unit is configured to obtain topography data of the specimen placed on the stage by illumination of a surface of the specimen with an optical signal, and a processor configured to generate a statistical data from the topography data and produce a defect notification if the statistical data is outside of a control limit.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 9, 2024
    Inventors: RICHARD PAUL GOOD, ROBERTO SCHIWON, MATTHIAS RUHM, DIRK WOLLSTEIN
  • Patent number: 8323471
    Abstract: A method of automatic deposition profile targeting for electrochemically depositing copper with a position-dependent controllable plating tool including the steps of depositing copper on a patterned product wafer, measuring an actual thickness profile of the deposited copper and generating respective measurement data, feeding the measurement data to an advanced process control (APC) model and calculating individual corrections for plating parameters in the position-dependent controllable plating tool.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: December 4, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Ortleb, Markus Nopper, Dirk Wollstein
  • Patent number: 8147670
    Abstract: The present disclosure generally addresses the problem of controlling a plating profile in multi-step recipes and addresses, in particular, the problem of compensating for variations of the plating tool state to stabilize the plating results. The compensation is done by adjustments of corrections factors for currents of a plating tool in a multi-anode configuration. The described method enables control of recipes with different current ratios in each recipe step and models different deposition sensitivities in each recipe step. Generally, the method of the present disclosure requires a measurement step, where the tool state is determined, and a data processing step, where the correction factors are set based on models describing the plating process and the tool state.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: April 3, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sylvia Boehlmann, Dirk Wollstein, Susanne Wehner
  • Publication number: 20090057153
    Abstract: The present disclosure generally addresses the problem of controlling a plating profile in multi-step recipes and addresses, in particular, the problem of compensating for variations of the plating tool state to stabilize the plating results. The compensation is done by adjustments of corrections factors for currents of a plating tool in a multi-anode configuration. The described method enables control of recipes with different current ratios in each recipe step and models different deposition sensitivities in each recipe step. Generally, the method of the present disclosure requires a measurement step, where the tool state is determined, and a data processing step, where the correction factors are set based on models describing the plating process and the tool sate.
    Type: Application
    Filed: May 13, 2008
    Publication date: March 5, 2009
    Inventors: Sylvia Boehlmann, Dirk Wollstein, Susanne Wehner
  • Publication number: 20090000950
    Abstract: A method of automatic deposition profile targeting for electrochemically depositing copper with a position-dependent controllable plating tool including the steps of depositing copper on a patterned product wafer, measuring an actual thickness profile of the deposited copper and generating respective measurement data, feeding the measurement data to an advanced process control (APC) model and calculating individual corrections for plating parameters in the position-dependent controllable plating tool.
    Type: Application
    Filed: February 21, 2008
    Publication date: January 1, 2009
    Inventors: Thomas Ortleb, Markus Nopper, Dirk Wollstein
  • Patent number: 7268000
    Abstract: A method and a controller for the chemical mechanical polishing (CMP) of substrates and, in particular, for the chemical mechanical polishing of metallization layers is disclosed. In a linear model of the CMP process, the erosion of the metallization layer to be treated is determined by the overpolish time and possibly by an extra polish time on a separate polishing platen for polishing the dielectric layer, wherein the CMP inherent characteristics are represented by sensitivity parameters derived empirically. Moreover, the control operation is designed so that even with a certain inaccuracy of the sensitivity parameters due to subtle process variations, a reasonable controller response is obtained.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: September 11, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dirk Wollstein, Jan Raebiger, Gerd Marxsen
  • Patent number: 6936480
    Abstract: An improved CMP controller allows the calculation of the polish time required for removing a patterned layer stack to a desired final thickness, wherein the initial layer thickness of each layer contained in the layer stack is employed. Moreover, a topography factor characterizing the surface structure of the layer stack and a selectivity characterizing the ratio of removal rates between adjacent material layers are used. Furthermore, a state variable of the controller represented by the removal rate of one of the layers may periodically be updated on the basis of the previously calculated polish time and a measurement value of the finally obtained layer thickness. The improved controller is particularly advantageous in the CMP process for STI isolation structures, in which the final thickness of a CMP stop layer, having a significantly reduced removal rate compared to the overlying dielectric layer, has to be precisely controlled.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: August 30, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dirk Wollstein, Stefan Lingel, Jan Räbiger
  • Publication number: 20050067290
    Abstract: An electroplating tool is operated in combination with a controller which automatically determines the individual currents for a multi-anode configuration of the plating tool. The calculation of the anode currents may be based on sensitivity data and measurement data as well as on a desired target profile, so that a fast response with respect to process variations may be achieved even for a plating tool including a plurality of process chambers.
    Type: Application
    Filed: June 4, 2004
    Publication date: March 31, 2005
    Inventors: Matthias Bonkass, Dirk Wollstein, Axel Preusse
  • Patent number: 6821859
    Abstract: Methods and systems are disclosed that allow an adjustment of an electrical property of a field effect transistor during the fabrication of the device. A manufacturing process downstream of the gate electrode formation step is controlled in response to the measured gate length such that a deviation of the measured gate length is, at least partially, compensated by a subsequent process step in order to maintain the electrical property of the completed field effect transistor within specified tolerances. In one illustrative embodiment, the effective gate length that is defined as the lateral distance of lightly doped regions is controlled so as to substantially maintain it. Moreover, a controller is disclosed that allows the manufacturing of a field effect transistor on a run-to-run basis by which variations of the gate length are at least partially compensated.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: November 23, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Raebiger, André Holfeld, Dirk Wollstein
  • Publication number: 20040023490
    Abstract: An improved CMP controller allows the calculation of the polish time required for removing a patterned layer stack to a desired final thickness, wherein the initial layer thickness of each layer contained in the layer stack is employed. Moreover, a topography factor characterizing the surface structure of the layer stack and a selectivity characterizing the ratio of removal rates between adjacent material layers are used. Furthermore, a state variable of the controller represented by the removal rate of one of the layers may periodically be updated on the basis of the previously calculated polish time and a measurement value of the finally obtained layer thickness. The improved controller is particularly advantageous in the CMP process for STI isolation structures, in which the final thickness of a CMP stop layer, having a significantly reduced removal rate compared to the overlying dielectric layer, has to be precisely controlled.
    Type: Application
    Filed: November 26, 2002
    Publication date: February 5, 2004
    Inventors: Dirk Wollstein, Stefan Lingel, Jan Rabiger
  • Publication number: 20030186546
    Abstract: A method and a controller for the chemical mechanical polishing (CMP) of substrates and, in particular, for the chemical mechanical polishing of metallization layers is disclosed. In a linear model of the CMP process, the erosion of the metallization layer to be treated is determined by the overpolish time and possibly by an extra polish time on a separate polishing platen for polishing the dielectric layer, wherein the CMP inherent characteristics are represented by sensitivity parameters derived empirically. Moreover, the control operation is designed so that even with a certain inaccuracy of the sensitivity parameters due to subtle process variations, a reasonable controller response is obtained.
    Type: Application
    Filed: September 30, 2002
    Publication date: October 2, 2003
    Inventors: Dirk Wollstein, Jan Raebiger, Gerd Marxsen
  • Publication number: 20030162341
    Abstract: Methods and systems are disclosed that allow an adjustment of an electrical property of a field effect transistor during the fabrication of the device. A manufacturing process downstream of the gate electrode formation step is controlled in response to the measured gate length such that a deviation of the measured gate length is, at least partially, compensated by a subsequent process step in order to maintain the electrical property of the completed field effect transistor within specified tolerances. In one illustrative embodiment, the effective gate length that is defined as the lateral distance of lightly doped regions is controlled so as to substantially maintain it. Moreover, a controller is disclosed that allows the manufacturing of a field effect transistor on a run-to-run basis by which variations of the gate length are at least partially compensated.
    Type: Application
    Filed: July 30, 2002
    Publication date: August 28, 2003
    Inventors: Jan Raebiger, Andre Holfeld, Dirk Wollstein