Abstract: A storage device maintains uniform write performance for data written to a memory device including varying block sizes. The storage device includes a balancing module to ensure that free blocks exist in a partition on the memory device and to define a garbage collection threshold based on blocks available in the partition. The storage device also includes a controller to receive host data from a host device, write the host data to the memory device; and relocate the host data in the memory device during a background operation. The controller initiates the background operation on the memory device at the garbage collection threshold and executes the background operation according to a host write-to-relocation write ratio based on a dynamically calculated size of the remaining free blocks in the partition.

Abstract: A storage device may use unused bits in a memory device communicatively coupled to the storage device to reduce resource usage and time on the storage device during background operations. The memory device includes a plane having a redundant column section including unused bits. When the storage device receives instructions from a host device, a controller on the storage device may determine that the instructions are associated with data to be discarded from the memory device and may associate the data to be discarded with fragments in the memory device. The controller may generate relocation information, associate the relocation information with data stored in the memory device, and store the relocation information in the unused bits. During relocation operations, the controller may use the relocation information to determine whether fragments in the memory device include the data to be discarded and/or whether to move data in the memory device.

Abstract: Aspects of a storage device for providing superior sustained sequential write (SSW) performance are disclosed. A controller on the storage device allocates buffer space in the host memory buffers (HMBs) on the host device for storage of relocation data, i.e., data to be folded or compacted. The controller or a hardware element therein can therefore allocate local SRAM (including TRAM) for use in accommodating incoming host writes. The increased SRAM allocation of relocation data without an attendant increase in cost or size to the storage device enables the storage device to perform operations in parallel and substantially increase SSW performance metrics.

Abstract: A storage device performs error handling using asymmetric blocks in a memory device. The memory may be divided into blocks of varying sizes. A controller on the storage device may process instructions by writing data to a first block on the memory device. If the controller determines an error occurred with a write operation to the first block and if the controller is unable to find a second block that is the same size as the first block, the controller may replace the first block with a second block that is larger than the first block. The controller may mark the second block and continue with the write operation.

Abstract: Storage devices contain a memory array that comprises memory devices for storing data. These memory devices can be arranged in a configuration of blocks that group a number of memory devices together. Often, blocks are the smallest unit that can be erased, however various storage devices can divide blocks into sub-blocks which can operate as unique blocks themselves. These sub-blocks can be seen as regular blocks to the storage device or host computer. However, the time needed to erase these increased number of operational sub-blocks decreases overall performance as more erase time is needed. Devices and methods described herein decrease overall erase times within a sub-block memory array by checking the status of related sub-blocks before processing an erase request for a particular sub-block. Each of the related sub-blocks can be erased alongside the particular sub-block if the status of the related sub-blocks provides for erasure without losing host data.

Abstract: A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.

Abstract: A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.

Abstract: Aspects of a storage device for providing superior sustained sequential write (SSW) performance are disclosed. A controller on the storage device allocates buffer space in the host memory buffers (HMBs) on the host device for storage of relocation data, i.e., data to be folded or compacted. The controller or a hardware element therein can therefore allocate local SRAM (including TRAM) for use in accommodating incoming host writes. The increased SRAM allocation of relocation data without an attendant increase in cost or size to the storage device enables the storage device to perform operations in parallel and substantially increase SSW performance metrics.