Abstract: A first memory instance comprises one or more first bitcell arrays and one or more peripheral circuits. The first memory instance further comprises a high-speed voltage monitoring circuit operable to monitor a supply voltage and a power down signal in the first memory instance, the high-speed voltage monitoring circuit further operable to provide an output power ready signal derived from the supply voltage and the power down signal such that the output power ready signal indicates when the power down signal is low and the supply voltage is high.

Abstract: Storage circuitry including a bitcell array including a plurality of bitcells arranged in one or more columns and one or more rows, a first bitline to select bitcells of a first column, a first dummy bitline associated with the first bitline, where the first dummy bitline includes dummy control circuitry having a plurality of electrical paths arranged between the dummy bitline and a first voltage level, where a first electrical path of the plurality of electrical paths includes a first load electrically couplable thereto to control a property of a dummy bitline signal.

Abstract: A circuit to precharge a dummy wordline includes a first branch comprising first and second PMOS devices; and a second branch comprising a single PMOS device. Also, in response to a power supply transition, the second branch can be configured to precharge the dummy wordline through the single PMOS device. Also, a method to precharge a dummy wordline includes: precharging, by a first branch of a circuit, a dummy wordline, and in response to a power supply transition, precharging the dummy wordline through a single PMOS device of a second branch of the circuit.

Abstract: Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuits comprising memory read output circuitry including a read signal input terminal, a latch, and a combinatorial gate coupled to the read signal input terminal and the latch.

Abstract: A first memory instance comprises one or more first bitcell arrays and one or more peripheral circuits. The first memory instance further comprises a high-speed voltage monitoring circuit operable to monitor a supply voltage and a power down signal in the first memory instance, the high-speed voltage monitoring circuit further operable to provide an output power ready signal derived from the supply voltage and the power down signal such that the output power ready signal indicates when the power down signal is low and the supply voltage is high.

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: Various implementations described herein are related to a device having an array of bitcells that are accessible via wordlines and bitlines including unselected bitlines and a selected bitline. Each bitcell in the array of bitcells may be selectable via a selected wordline of the wordlines and the selected bitline of the bitlines. The device may include precharge circuitry that is configured to selectively precharge the unselected bitlines and the selected bitline before arrival of a wordline signal on the selected wordline.

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: Various implementations described herein are related to a device having a sense amplifier with multiple output ports. The device may include tri-state buffer circuitry having multiple tri-state buffers coupled to the multiple output ports of the sense amplifier. The device may include latch circuitry having multiple latches coupled to the multiple tri-state buffers of the tri-state buffer circuitry.

Abstract: Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage range based on the input data signal and the output data signal. An output circuit of the device toggles the output data signal between a logical zero of the second voltage range and a logical one of the second voltage range based on the first internal signal, the second internal signal, and a compliment of the input data signal.

Abstract: Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage range based on the input data signal and the output data signal. An output circuit of the device toggles the output data signal between a logical zero of the second voltage range and a logical one of the second voltage range based on the first internal signal, the second internal signal, and a compliment of the input data signal.

Abstract: A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.

Abstract: A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.

Abstract: Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.

Abstract: Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.

Abstract: A sense amplifier enable signal delay circuit for the programmable control of the delay of the generation of a sense amplifier enable signal is described. Further, stacked transistors and a pulse-width control block, which are programmed by external test pins to control the delay of the generation of a sense amplifier enable signal are described. Methods associated with the use of the sense amplifier enable signal delay circuit and for the sense amplifier enable signal generation delay are also described.