Abstract: This application discloses a method and system of using HMB as a cache of physical address mapping table. The method comprises: arranging physical addresses in order of logical addresses, physical mapping entries corresponding to a plurality of consecutive physical addresses form one table unit, and a logical address corresponding to a first entry of each table unit is used as an index of the table unit; determining HMB size, dividing all table units into a plurality of sections according to the HMB size, each section comprises a plurality of table units, each section is divided into a plurality of ways; calculating a metadata according to logical address corresponding to the first entry of the table unit to be stored and the HMB size, the metadata comprises a section number and a way number; writing the metadata and the table unit to be stored into the HMB. This application uses HMB as L2P address mapping table cache of SSD controller, saving or avoiding use cost of DRAM on SSD, and reducing SSD size.

Abstract: The present disclosure relates to a method and a device for processing a read command, a controller, and a storage medium, comprising determining at least one read command and a command index number; acquiring a flash memory data unit and data unit information corresponding to each of the read commands, the data unit information comprising a data unit index number and the command index number; searching for a corresponding address entry in an address entry buffer based on the data unit information, the address entry buffer comprising at least one buffer unit storing the address entry with the corresponding data unit information; and in response to finding an address entry corresponding to the data unit information, transmitting the flash memory data unit to a corresponding host memory address in the address entry and storing the flash memory data unit therein.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: In an example, a method of processing commands for a non-volatile storage device includes storing the commands among a plurality of first-level queues in a random access memory (RAM). Each command is assigned to a first-level queue based on membership in one of a plurality of first-level categories. The method further includes removing selected commands from the plurality of first-level queues according to a first schedule and performing at least one operation on the selected commands. The method further includes storing the selected commands among a plurality of second-level queues in the RAM. Each selected command is assigned to a second-level queue based on whether the command is a read command or a write command. The method further includes removing active commands from the plurality of second-level queues according to a second schedule. The method further includes issuing the active commands to a back end of the controller for processing.

Abstract: A technique for sharing resources in a data storage device. The data storage device receives a command associated with a non-volatile semiconductor memory device from a host system, the command including a virtual function identifier and a transaction identifier. The data storage device identifies, via a virtual function mapping unit that is included within a controller and that maintains a function mapping table which stores programmable values that associate virtual functions with portions of shared resources of the controller, a portion of a shared resource of the controller based on the virtual function identifier and the transaction identifier. The data storage device accesses the identified portion of the shared resource based on the received command.

Abstract: A technique for sharing resources in a data storage device. The data storage device receives a command associated with a non-volatile semiconductor memory device from a host system, the command including a virtual function identifier and a transaction identifier. The data storage device identifies, via a virtual function mapping unit that is included within a controller and that maintains a function mapping table which stores programmable values that associate virtual functions with portions of shared resources of the controller, a portion of a shared resource of the controller based on the virtual function identifier and the transaction identifier. The data storage device accesses the identified portion of the shared resource based on the received command.

Abstract: A technique for sharing resources in a data storage device. The data storage device receives a command associated with a non-volatile semiconductor memory device from a host system, the command including a virtual function identifier and a transaction identifier. The data storage device identifies, via a virtual function mapping unit that is included within a controller and that maintains a function mapping table which stores programmable values that associate virtual functions with portions of shared resources of the controller, a portion of a shared resource of the controller based on the virtual function identifier and the transaction identifier. The data storage device accesses the identified portion of the shared resource based on the received command.

Abstract: In an example, a method of fetching direct memory access (DMA) descriptors for commands to a non-volatile semiconductor storage device includes storing the commands among a plurality of queues in a command random access memory (RAM). The method further includes processing one or more of the commands from the plurality of queues and issuing requests to read from or write into the non-volatile semiconductor storage device according to the processing. The method further includes fetching DMA descriptors from the host system for the processed commands according to a real-time fetch quota. The method further includes pre-fetching DMA descriptors from the host system for queued commands that are not being processed according to a pre-fetch quota. The method further includes storing fetched and pre-fetched DMA descriptors in a descriptor RAM.

Abstract: A data storage device includes a non-volatile semiconductor storage device and a controller that is configured to perform interleaving of small reads with large reads and small writes with large writes. In the example of reads, the controller receives a sequence of read commands including a first read command having a read size larger than a read threshold size and a second read command having a read size smaller than the read threshold size, and issue first and second read requests in succession to read data of a predetermined size less than the read threshold size, from the non-volatile semiconductor storage device. The interleaving is achieved by issuing the first read request to execute the first read command and the second read request to execute the second read command. As a result of this interleaving, the second read command will have a chance to complete earlier than the first read command even though it was received by the controller later in time.

Abstract: A system including a controller and a bridge module. The controller is configured to (i) communicate with a host via a first interface, and (ii) communicate with a storage device via a second interface. The second interface is separate from the first interface. The bridge module is configured to allow the controller to transfer data between the storage device and the host without buffering the data, and to access a memory of the host via the first interface during the transfer.

Abstract: In an example, a method of fetching direct memory access (DMA) descriptors for commands to a non-volatile semiconductor storage device includes storing the commands among a plurality of queues in a command random access memory (RAM). The method further includes processing one or more of the commands from the plurality of queues and issuing requests to read from or write into the non-volatile semiconductor storage device according to the processing. The method further includes fetching DMA descriptors from the host system for the processed commands according to a real-time fetch quota. The method further includes pre-fetching DMA descriptors from the host system for queued commands that are not being processed according to a pre-fetch quota. The method further includes storing fetched and pre-fetched DMA descriptors in a descriptor RAM.

Abstract: In an example, a method of processing commands for a non-volatile storage device includes storing the commands among a plurality of first-level queues in a random access memory (RAM). Each command is assigned to a first-level queue based on membership in one of a plurality of first-level categories. The method further includes removing selected commands from the plurality of first-level queues according to a first schedule and performing at least one operation on the selected commands. The method further includes storing the selected commands among a plurality of second-level queues in the RAM. Each selected command is assigned to a second-level queue based on whether the command is a read command or a write command. The method further includes removing active commands from the plurality of second-level queues according to a second schedule. The method further includes issuing the active commands to a back end of the controller for processing.

Abstract: A data storage device includes a non-volatile semiconductor storage device and a controller that is configured to perform interleaving of small reads with large reads and small writes with large writes. In the example of reads, the controller receives a sequence of read commands including a first read command having a read size larger than a read threshold size and a second read command having a read size smaller than the read threshold size, and issue first and second read requests in succession to read data of a predetermined size less than the read threshold size, from the non-volatile semiconductor storage device. The interleaving is achieved by issuing the first read request to execute the first read command and the second read request to execute the second read command. As a result of this interleaving, the second read command will have a chance to complete earlier than the first read command even though it was received by the controller later in time.

Abstract: A technique for sharing resources in a data storage device. The data storage device receives a command associated with a non-volatile semiconductor memory device from a host system, the command including a virtual function identifier and a transaction identifier. The data storage device identifies, via a virtual function mapping unit that is included within a controller and that maintains a function mapping table which stores programmable values that associate virtual functions with portions of shared resources of the controller, a portion of a shared resource of the controller based on the virtual function identifier and the transaction identifier. The data storage device accesses the identified portion of the shared resource based on the received command.

Abstract: The present disclosure includes systems and techniques relating to effectively increasing a command queue length for accessing storage, such as by increasing the Queuing Depth (Q-Depth) of Native Command Queuing (NCQ) Commands. In some implementations, a method can comprise receiving a first command to access a first memory location of a storage device; receiving a second command to access a second memory location of a storage device; constructing a consolidated command including a memory address and a data transfer count associated with each of the first command and the second command; constructing an information command having consolidation information about the consolidated command; and communicating the information command and the consolidated command to the storage device for processing by the storage device.

Abstract: A system including a controller and a bridge module. The controller is configured to (i) communicate with a host via a first interface, and (ii) communicate with a storage device via a second interface. The second interface is separate from the first interface. The bridge module is configured to allow the controller to transfer data between the storage device and the host without buffering the data, and to access a memory of the host via the first interface during the transfer.

Abstract: A system including a first controller configured to communicate with a host via a first interface; a second controller configured to communicate with a storage device via a second interface, where the second interface is different than the first interface; and a bridge module configured to allow the second controller to transfer data between the storage device and the host and to allow the second controller to access memory of the host via the first interface during the transfer.