Patents by Inventor Divya K. Joshi

Divya K. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Determine soft error resilience while verifying architectural compliance
    Patent number: 10896118
    Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ophir Erez, Bodo Hoppe, Divya K. Joshi, Gerrit Koch, Parminder Singh
  • DETERMINE SOFT ERROR RESILIENCE WHILE VERIFYING ARCHITECTURAL COMPLIANCE
    Publication number: 20190227906
    Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Ophir Erez, Bodo Hoppe, Divya K. Joshi, Gerrit Koch, Parminder Singh
  • Determine soft error resilience while verifying architectural compliance
    Patent number: 10318406
    Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ophir Erez, Bodo Hoppe, Divya K. Joshi, Gerrit Koch, Parminder Singh
  • DETERMINE SOFT ERROR RESILIENCE WHILE VERIFYING ARCHITECTURAL COMPLIANCE
    Publication number: 20180239691
    Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 23, 2018
    Inventors: Ophir Erez, Bodo Hoppe, Divya K. Joshi, Gerrit Koch, Parminder Singh