Abstract: A circuit (70) includes a voltage reference circuit (72) that includes an output terminal (74), wherein the voltage reference circuit (72) is configured to generate an output voltage at the output terminal (74) having a first transfer function of voltage with respect to strain. The circuit (70) also includes a strain compensation circuit (78) having an input terminal connected to the output terminal (74) of the voltage reference circuit, and having a strain compensation circuit output terminal (80). The strain compensation circuit (78) is configured to receive the output voltage comprising the first transfer function at the input terminal. The strain compensation circuit (78) has a second transfer function of voltage with respect to strain that is substantially opposite that of the first transfer function, thereby outputting a compensated voltage at the strain compensation circuit output terminal (80) that is substantially independent of strain.

Abstract: In some examples, a circuit includes a first electrical component disposed in a first region of a substrate. The circuit also includes a first measurement circuit disposed in the first region proximate to the first electrical component. The circuit also includes a second electrical component disposed in a second region of the substrate, the second region of the substrate proximate to the first region of the substrate. The circuit also includes a second measurement circuit disposed in the second region proximate to the second electrical component. The circuit also includes a stress induction device disposed on the substrate above the second region.

Abstract: An example multi-mode voltage regulator is described. The voltage regulator can have an output terminal. The voltage regulator can include a mode detector that can be configured to determine whether an inductive element is coupled to the output terminal based on an amount of inductance at the output terminal. The mode detector is configured to set the voltage regulator to operate in either a buck mode of operation or a linear dropout (LDO) mode of operation based on the amount of inductance at the output terminal.

Abstract: Load sharing techniques for voltage regulators. In an example, the techniques may be implemented in an LDO voltage regulator configured to provide load sharing with a single driver for internal and external pass elements using a pair of variable voltage dividers to adjust the load sharing based on load current. In other examples, a calibrated voltage source can be used to replace one of the variable voltage dividers. Calibration circuitry and methodologies for determining the value of the calibrated voltage source are also described. In still other examples, a single variable voltage divider can be used, with no calibrated voltage source, by constraining the external pass element to be weaker than the internal pass element. In any such examples, the internal and external pass elements can be implemented, for instance, with either n-type or p-type power transistors, and with similar transistor technologies or diverse transistor technologies (e.g., FETs and BJTs).

Abstract: Load sharing techniques for voltage regulators. In an example, the techniques may be implemented in an LDO voltage regulator configured to provide load sharing with a single driver for internal and external pass elements using a pair of variable voltage dividers to adjust the load sharing based on load current. In other examples, a calibrated voltage source can be used to replace one of the variable voltage dividers. Calibration circuitry and methodologies for determining the value of the calibrated voltage source are also described. In still other examples, a single variable voltage divider can be used, with no calibrated voltage source, by constraining the external pass element to be weaker than the internal pass element. In any such examples, the internal and external pass elements can be implemented, for instance, with either n-type or p-type power transistors, and with similar transistor technologies or diverse transistor technologies (e.g., FETs and BJTs).

Abstract: Load sharing techniques for voltage regulators. In an example, the techniques may be implemented in an LDO voltage regulator configured to provide load sharing with a single driver for internal and external pass elements using a pair of variable voltage dividers to adjust the load sharing based on load current. In other examples, a calibrated voltage source can be used to replace one of the variable voltage dividers. Calibration circuitry and methodologies for determining the value of the calibrated voltage source are also described. In still other examples, a single variable voltage divider can be used, with no calibrated voltage source, by constraining the external pass element to be weaker than the internal pass element. In any such examples, the internal and external pass elements can be implemented, for instance, with either n-type or p-type power transistors, and with similar transistor technologies or diverse transistor technologies (e.g., FETs and BJTs).

Abstract: An example system includes a first battery; a second battery; a switch coupled to the first battery and the second battery, the switch configured to, based on a control signal, connect or disconnect at least one of the first battery from a load or the second battery from a load; and a current sensor to generate the control signal, the current sensor including a first sensor input terminal and a second sensor input terminal; and an amplifier configured to operate as an amplifier to determine an amount of current between the first sensor input terminal and the second sensor input terminal; and operate as a comparator to determine a direction of the current between the first sensor input terminal and the second sensor input terminal, the control signal corresponding to at least one of the amount of current or the direction of the current.

Abstract: A float detector includes a latch and a float detection circuit. The latch includes a latch output and an input/output (I/O) terminal. The I/O terminal is coupled to an input terminal. The float detection circuit includes a detection input, a drive output, and a float detection circuit. The detection input is coupled to the latch output. The drive output is coupled to the I/O terminal. The float detector is configured to provide a drive signal at the drive output, and determine that the input terminal is floating based on a latch output signal received at the detection input responsive to the drive signal.

Abstract: Some aspects relate to a circuit comprising a temperature-dependent circuit, a proportional to absolute temperature (PTAT) current sink, a complementary to absolute temperature current source (CTAT) current source, and a heating element. The temperature-dependent circuit is disposed within an integrated circuit package. The PTAT current sink is disposed within the integrated circuit package and has an output terminal. The CTAT current source is disposed within the integrated circuit package and has an output terminal coupled to the output terminal of the PTAT current sink. The heating element is disposed within the integrated circuit package and has a control terminal coupled to the output terminal of the PTAT current sink and the output terminal of the CTAT current source.

Abstract: In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. A voltage divider network is coupled to the second stage. The circuit includes an output transistor having first and second terminals, in which the first terminal of the output transistor is coupled to the first stage, and the second terminal of the output transistor is coupled to the voltage divider network.

Abstract: A circuit (70) includes a voltage reference circuit (72) that includes an output terminal (74), wherein the voltage reference circuit (72) is configured to generate an output voltage at the output terminal (74) having a first transfer function of voltage with respect to strain. The circuit (70) also includes a strain compensation circuit (78) having an input terminal connected to the output terminal (74) of the voltage reference circuit, and having a strain compensation circuit output terminal (80). The strain compensation circuit (78) is configured to receive the output voltage comprising the first transfer function at the input terminal. The strain compensation circuit (78) has a second transfer function of voltage with respect to strain that is substantially opposite that of the first transfer function, thereby outputting a compensated voltage at the strain compensation circuit output terminal (80) that is substantially independent of strain.

Abstract: In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. A voltage divider network is coupled to the second stage. The circuit includes an output transistor having first and second terminals, in which the first terminal of the output transistor is coupled to the first stage, and the second terminal of the output transistor is coupled to the voltage divider network.

Abstract: Techniques for providing amplifier overdrive protection. In an example, a circuit configured to determine the difference between the amplifier output voltage and the amplifier power supply voltage, so as to sense an overdrive condition. Responsive to the difference exceeding a threshold, the circuit is configured to limit the amplifier drive capability, which in turn limits the maximum amplifier output current. The circuit may restore the amplifier drive capability, responsive to cessation of the overdrive condition. In some such cases, the circuit may be configured with hysteresis, so as to provide stability when transitioning to and from the reduced drive state. Another example circuit operates in a similar fashion but is configured to determine the difference between the amplifier input voltage and a reference voltage, so as to sense an overdrive condition. In some such cases, the reference voltage may be equal to amplifier power supply voltage divided by amplifier gain.

Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

Abstract: A circuit includes a load circuit and a voltage regulator circuit. The load circuit includes a load voltage input, a first transistor and a second transistor. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage. The voltage regulator circuit includes a load voltage output and a tracking circuit. The load voltage output is coupled to the load voltage input. The tracking circuit is configured to provide a load voltage at the load voltage output in which the load voltage tracks the first threshold voltage and the second threshold voltage.

Abstract: A float detector includes a latch and a float detection circuit. The latch includes a latch output and an input/output (I/O) terminal. The I/O terminal is coupled to an input terminal. The float detection circuit includes a detection input, a drive output, and a float detection circuit. The detection input is coupled to the latch output. The drive output is coupled to the I/O terminal. The float detector is configured to provide a drive signal at the drive output, and determine that the input terminal is floating based on a latch output signal received at the detection input responsive to the drive signal.

Abstract: In described examples, a circuit includes a switch. The switch includes first transistors and second transistors. A voltage generation circuit is coupled to the switch. A level shifter is coupled to the voltage generation circuit and is configured to receive a control signal. A logic unit is coupled to the level shifter and the voltage generation circuit. The logic unit is configured to generate a secondary signal. The first transistors are configured to receive the control signal, and the second transistors are configured to receive the secondary signal.

Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

Abstract: In described examples, a circuit includes a switch. The switch includes first transistors and second transistors. A voltage generation circuit is coupled to the switch. A level shifter is coupled to the voltage generation circuit and is configured to receive a control signal. A logic unit is coupled to the level shifter and the voltage generation circuit. The logic unit is configured to generate a secondary signal. The first transistors are configured to receive the control signal, and the second transistors are configured to receive the secondary signal.