Abstract: Aspects of the present disclosure relate to proactive intervention in a software application. Embodiments include selecting, by a proactive intervention system related to an application, an event of a plurality of events related to use of the application for processing based on event priorities associated with the plurality of events. Embodiments further include receiving, by the proactive intervention system, contextual information related to the event. Embodiments further include determining, by the proactive intervention system, a proactive intervention based on the event and the contextual information. Embodiments further include determining, by the proactive intervention system, that the proactive intervention can presently be provided based on intervention availability data. Embodiments further include providing, by the proactive intervention system, the proactive intervention via a user interface associated with the application.

Abstract: A cloud-based personalization service utilizes a personalization model providing service users with tools to create, personalize, and manage their own user profiles, which are abstracted in the form of “personas,” that can learn from, and be shared across, different ecosystems of online services and applications. One or more personas may be locally instantiated on the user's various computing devices by a personalization system. The personalization service and system interoperate to enable users to set operating parameters, preferences, and content-filtering criteria for their personas. Users can strictly control the information and parameters that their personas expose to the services and applications to protect user privacy and enhance the quality of online interactions. The personalization model facilitates personalization of the user's personas to individual online services and applications based on context-awareness to further improve the relevance of delivered content and user experiences.

Abstract: Aspects of the present disclosure relate to proactive intervention in a software application. Embodiments include selecting, by a proactive intervention system related to an application, an event of a plurality of events related to use of the application for processing based on event priorities associated with the plurality of events. Embodiments further include receiving, by the proactive intervention system, contextual information related to the event. Embodiments further include determining, by the proactive intervention system, a proactive intervention based on the event and the contextual information. Embodiments further include determining, by the proactive intervention system, that the proactive intervention can presently be provided based on intervention availability data. Embodiments further include providing, by the proactive intervention system, the proactive intervention via a user interface associated with the application.

Abstract: A method and system monitors activity of a user of a data management system and detects a trigger event in the activity of the user. The method and system generates a support case responsive to the trigger event. The support case includes support rules defining what types of the user's personal data will be accessible to an assistance agent when the user requests assistance related to the trigger event. The method and system utilizes machine learning processes to determine what types of user related data should be accessible to assistance agents in support cases.

Abstract: In one example, a presentation control device may allow a presenter, such as a teacher, to control interactions between audience members and the presenter. The presentation control device may display a presentation controlled by a presenter to a presentation audience as part of a group presentation session. The presentation control device may receive from the presenter a communication rule controlling an interaction between an audience member device and the presentation control device as part of controlling the presentation. The presentation control device may receive a communication regarding the presentation from an audience member in the presentation audience via the audience member device. The presentation control device direct the communication based on the communication rule.

Abstract: In one example, a presentation control device may allow a presenter, such as a teacher, to control interactions between audience members and the presenter. The presentation control device may display a presentation controlled by a presenter to a presentation audience as part of a group presentation session. The presentation control device may receive from the presenter a communication rule controlling an interaction between an audience member device and the presentation control device as part of controlling the presentation. The presentation control device may receive a communication regarding the presentation from an audience member in the presentation audience via the audience member device. The presentation control device direct the communication based on the communication rule.

Abstract: An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.

Abstract: An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.

Abstract: A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.

Abstract: A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.

Abstract: A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.

Abstract: A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.

Abstract: A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.

Abstract: A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.