Patents by Inventor Divya MANI
Divya MANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830783Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.Type: GrantFiled: October 11, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Aastha Uppal, Divya Mani, Je-Young Chang
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Patent number: 11640929Abstract: An integrated circuit assembly may be formed having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core, and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.Type: GrantFiled: December 20, 2018Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Divya Mani, Nicholas Haehn
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Patent number: 11581240Abstract: An integrated circuit package that includes a liquid phase thermal interface material (TIM) is described. The package may include any number of die. The liquid phase TIM can be sealed in a chamber between a die and an integrated heat spreader and bounded on the sides by a perimeter layer. The liquid phase TIM can be fixed in place or circulated, depending on application. A thermal conductivity of the liquid phase TIM can be at least 15 Watts/meter-Kelvin, according to some embodiments. A liquid phase TIM eliminates failure mechanisms present in solid phase TIMs, such as cracking due to warpage and uncontained flow out of the module.Type: GrantFiled: December 21, 2018Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Kedar Dhane, Omkar Karhade, Aravindha R. Antoniswamy, Divya Mani
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Publication number: 20220256715Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.Type: ApplicationFiled: July 30, 2021Publication date: August 11, 2022Inventors: Divya MANI, William J. LAMBERT, Shawna LIFF, Sergio A. CHAN ARGUEDAS, Robert L. SANKMAN
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Patent number: 11112841Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.Type: GrantFiled: April 1, 2017Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Divya Mani, William J. Lambert, Shawna Liff, Sergio A. Chan Arguedas, Robert L. Sankman
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Publication number: 20210259134Abstract: Embodiments disclosed herein include an integrated heat spreader (IHS). In an embodiment, the IHS comprises a main body, where the main body comprises a first surface and a second surface opposite from the second surface. In an embodiment, the IHS further and a support extending from the first surface of the main body. In an embodiment, the support comprises a shell, and a layer over an interior surface of the shell.Type: ApplicationFiled: February 19, 2020Publication date: August 19, 2021Inventors: Aastha UPPAL, Divya MANI, Je-Young CHANG
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Publication number: 20210111091Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.Type: ApplicationFiled: October 11, 2019Publication date: April 15, 2021Inventors: Aastha UPPAL, Divya MANI, Je-Young CHANG
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Publication number: 20200219789Abstract: An integrated circuit structure may be formed using a phase change material to substantially fill at least one chamber within the integrated circuit assembly to increase thermal capacitance. The integrated circuit assembly may comprise a substrate, at least one integrated circuit device electrically attached to the substrate, a heat dissipation device, a thermal interface material between the integrated circuit device and the heat dissipation device, a chamber defined by the heat dissipation device, the substrate, and the integrated circuit device, and a phase change material within the chamber.Type: ApplicationFiled: January 7, 2019Publication date: July 9, 2020Applicant: Intel CorporationInventors: Aastha Uppal, Je-Young Chang, Javed Shaikh, Divya Mani, Weihua Tang
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Publication number: 20200203254Abstract: An integrated circuit package that includes a liquid phase thermal interface material (TIM) is described. The package may include any number of die. The liquid phase TIM can be sealed in a chamber between a die and an integrated heat spreader and bounded on the sides by a perimeter layer. The liquid phase TIM can be fixed in place or circulated, depending on application. A thermal conductivity of the liquid phase TIM can be at least 15 Watts/meter-Kelvin, according to some embodiments. A liquid phase TIM eliminates failure mechanisms present in solid phase TIMs, such as cracking due to warpage and uncontained flow out of the module.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Applicant: INTEL CORPORATIONInventors: Kedar Dhane, Omkar Karhade, Aravindha R. Antoniswamy, Divya Mani
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Publication number: 20200203256Abstract: An integrated circuit assembly may be formed having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core, and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Applicant: Intel CorporationInventors: Nicholas Neal, Divya Mani, Nicholas Haehn
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Publication number: 20190377392Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.Type: ApplicationFiled: April 1, 2017Publication date: December 12, 2019Inventors: Divya MANI, William J. LAMBERT, Shawna LIFF, Sergio A. CHAN ARGUEDAS, Robert L. SANKMAN