Patents by Inventor Divya Pathak

Divya Pathak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200019224
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Application
    Filed: August 14, 2019
    Publication date: January 16, 2020
    Inventors: Pierce I-Jen Chuang, Phillip J. Restle, Christos Vezyrtzis, Divya Pathak
  • Publication number: 20190393360
    Abstract: The increasing power density and, therefore, current consumption of high performance integrated circuits (ICs) results in increased challenges in the design of a reliable and efficient on-chip power delivery network. In particular, meeting the stringent on-chip impedance of the IC requires circuit and system techniques to mitigate high frequency noise that results due to resonance between the package inductance and the onchip capacitance. In this paper, a novel circuit technique is proposed to suppress high frequency noise through the use of a hyperabrupt junction tuning varactor diode as a decoupling capacitor for noise critical functional blocks. With the proposed circuit technique, the voltage droops and overshoots on the onchip power distribution network are suppressed by up to 60% as compared to MIM or deep trench decoupling capacitors of the same capacitance.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 26, 2019
    Applicant: Drexel University
    Inventors: Divya Pathak, Ioannis Savidis
  • Patent number: 10437311
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pierce I. Chuang, Divya Pathak, Phillip J. Restle, Christos Vezyrtzis
  • Publication number: 20180314308
    Abstract: A real-time workload scheduling heuristic assigns tasks to the cores such that the total load current consumption of the cores is always less than the total current capability of the under-provisioned on-chip voltage regulators. In addition, the energy-efficient scheduling of the tasks on to the cores ensures that the reconfiguration of the power delivery network is minimized. The heuristic includes DVFS management based on the unique constraints of the under provisioned voltage regulators.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 1, 2018
    Applicants: Drexel University, George Mason University
    Inventors: Ioannis Savidis, Divya Pathak, Houman Homayoun
  • Publication number: 20180067532
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Inventors: PIERCE I. CHUANG, DIVYA PATHAK, PHILLIP J. RESTLE, CHRISTOS VEZYRTZIS
  • Patent number: 9912325
    Abstract: A circuit that detects the power supply voltage requirement of each voltage domain in an IC includes 1) a ring oscillator in each voltage domain, and 2) a power module. Two different circuit implementations of the power module may provide a precise reference voltage to on-chip voltage regulators (LDO or DC-DC switching buck converter). The power module supports DVFS and can provide the desired power supply voltage for advanced CMOS technology nodes (45 nm and beyond) in less than 100 ns. The voltage detection circuit clamps the voltage to the desired level to address power supply voltage variations due to PVT and ageing. The proposed technique has minimal power and area overhead to compensate for the power supply voltage variation, thus reducing power supply voltage margins which yields higher power saving.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: March 6, 2018
    Assignee: Drexel University
    Inventors: Ioannis Savidis, Divya Pathak
  • Publication number: 20160301400
    Abstract: A circuit that detects the power supply voltage requirement of each voltage domain in an IC includes 1) a ring oscillator in each voltage domain, and 2) a power module. Two different circuit implementations of the power module may provide a precise reference voltage to on-chip voltage regulators (LDO or DC-DC switching buck converter). The power module supports DVFS and can provide the desired power supply voltage for advanced CMOS technology nodes (45 nm and beyond) in less than 100 ns. The voltage detection circuit clamps the voltage to the desired level to address power supply voltage variations due to PVT and ageing. The proposed technique has minimal power and area overhead to compensate for the power supply voltage variation, thus reducing power supply voltage margins which yields higher power saving.
    Type: Application
    Filed: April 11, 2016
    Publication date: October 13, 2016
    Inventors: Ioannis Savidis, Divya Pathak