Patents by Inventor Divya Pisharoty

Divya Pisharoty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Gate structures for transistor devices for CMOS applications and products
    Patent number: 9362283
    Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
  • Methods for fabricating integrated circuits including fluorine incorporation
    Patent number: 9196475
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 24, 2015
    Assignees: GLOBALFOUNDRIES, INC., INTERMOLECULAR, INC.
    Inventors: Bongki Lee, Paul Besser, Kevin Kashefi, Olov Karlsson, Ashish Bodke, Ratsamee Limdulpaiboon, Divya Pisharoty, Nobi Fuchigami
  • METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS
    Publication number: 20150311206
    Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.
    Type: Application
    Filed: July 7, 2015
    Publication date: October 29, 2015
    Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
  • METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FLUORINE INCORPORATION
    Publication number: 20150303057
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 22, 2015
    Applicants: GLOBALFOUNDRIES, Inc., Intermolecular, Inc.
    Inventors: Bongki Lee, Paul Besser, Kevin Kashefi, Olov Karlsson, Ashish Bodke, Ratsamee Limdulpaiboon, Divya Pisharoty, Nobi Fuchigami
  • Methods of forming gate structures for transistor devices for CMOS applications
    Patent number: 9105497
    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: August 11, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
  • METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS
    Publication number: 20150061027
    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 5, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim