Abstract: Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the FAU to the PIC die. In another embodiment, a warpage amount of a PIC die is characterized, and a FAU lid with a similar warpage is fabricated, allowing for the FAU to position fibers correctly relative to waveguides in the PIC die. In another embodiment, a FAU has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.

Abstract: Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical couplers that provide optical coupling at or proximate to an edge of a silicon photonics package, to allow the package to optically couple with other devices or peripherals. In embodiments, the active optical coupler is optically coupled with a photonics IC (PIC) inside the photonics package, and provides an optical coupling mechanism for optical pathways outside the photonics package. The active optical coupler may include electrical circuitry and may be coupled to the package substrate to provide data related to the operation of the active optical coupler. Other embodiments may be described and/or claimed.

Abstract: A system enables optical communication with direct conversion of the electrical signal into an optical signal with an array of optical sources. The use of the array of optical sources can eliminate the need for a large serializer/deserializer (SERDES). With an array of optical sources, the optical communication can occur at lower power and lower frequency per optical source, with multiple parallel optical sources combining to provide a signal.

Abstract: A fluid compatible electro-optical packages and associated systems and devices are shown. For example, a fluid compatible electro-optical package includes integrated circuits with at least one photonic die and optical connections coupled with the integrated circuit. In an example, optical fibers are coupled with the optical connection. In an example fluid compatible electro-optical package, a fluid impermeable port is coupled with the optical connection and the optical fibers couple with the optical connection within the fluid impermeable port.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to enable customization of pigtail lengths of optical connectors. Disclosed is an apparatus comprising an affixed fiber array unit plug including a first optical fiber, a detachable fiber array unit plug including a second optical fiber, the detachable fiber array unit plug to be removably coupled to the affixed fiber array unit plug, and guide pins to interface with both the detachable fiber array unit plug and the affixed fiber array unit plug when coupled together, the guide pins to facilitate alignment of the first optical fiber with the second optical fiber.

Abstract: Embodiments disclosed herein include photonics packages. In an embodiment, a photonics package comprises a photonics die and a plurality of v-grooves on the photonics die. In an embodiment, a lens array is optically coupled to a spot size converter on the photonics die. In an embodiment, the lens array comprises a main body and a plurality of lenses extending out from the main body.

Abstract: Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.

Abstract: Embodiments disclosed herein include photonics systems and packages. In an embodiment, a photonics package comprises a package substrate and a photonics die overhanging an edge of the package substrate. In an embodiment, the photonics die comprises a v-groove for receiving an optical fiber. In an embodiment, the photonics package further comprises an integrated heat spreader (IHS) over the photonics die. In an embodiment, the IHS comprises a foot, and a hole through the foot is aligned with the v-groove.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical couplers that provide optical coupling at or proximate to an edge of a silicon photonics package, to allow the package to optically couple with other devices or peripherals. In embodiments, the active optical coupler is optically coupled with a photonics IC (PIC) inside the photonics package, and provides an optical coupling mechanism for optical pathways outside the photonics package. The active optical coupler may include electrical circuitry and may be coupled to the package substrate to provide data related to the operation of the active optical coupler. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include photonics packages. In an embodiment, a photonics package comprises a package substrate, and a compute die over the package substrate. In an embodiment, a photonics die is also over the package substrate, and the photonics die overhangs an edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the photonics die, and a fiber connector is coupled to the photonics die.

Abstract: Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

Abstract: A method for anonymizing data includes receiving call data of a call in an interaction recording system located behind a firewall of an internal network sub-environment, and within the internal network sub-environment: (i) storing the call data including interaction metadata, (ii) generating a speech-to-text transcript corresponding to words spoken by one or more callers, and (iii) generating an anonymized transcript by anonymizing personally identifiable information. A computing system includes a processor, and a memory including computer executable instructions that, when executed by the one processor, cause the system to perform the method. A non-transitory computer readable medium contains program instructions that when executed, cause a computer system to perform the method.

Abstract: A confidential sentiment analysis method includes receiving call data, storing the call data including interaction metadata, generating a speech-to-text transcript corresponding to words spoken by one or more callers, generating an anonymized transcript by anonymizing personally identifiable words, and generating a sentiment score by analyzing the anonymized transcript. A computing system includes a processor, and a memory including computer executable instructions that, when executed by the one processor, cause the system to receive call data, store the call data, generate a speech-to-text transcript, generate an anonymized transcript by anonymizing personally identifiable words, and generate a sentiment score based on the anonymized transcript.

Abstract: In some examples, a display includes a plurality of display pixels. Each display pixel includes one or more light emitters. At least some of the plurality of display pixels also includes a light detector.

Abstract: In some examples, a display includes a plurality of display pixels. Each display pixel includes one or more light emitters. At least some of the plurality of display pixels also includes a light detector.

Abstract: A method of evaluating a capacitive interface including discharging the capacitive interface to a lower voltage, timing while applying a unit charge to the capacitive interface until a voltage of the capacitive interface rises to a reference voltage and determining a corresponding charge time value, charging the capacitive interface to an upper voltage that is greater than the reference voltage, and timing while removing the unit charge from the capacitive interface until a voltage of the capacitive interface falls to the reference voltage and determining a corresponding discharge time value. The charge and discharge time values may be used to evaluate the capacitive interface by determining capacitance and leakage current. The time values may be determined using a counter. A capacitive interface evaluation system for evaluating the capacitive interface may include a charge circuit, a comparator, a counter and a controller.

Abstract: An integrated circuit, such as for example an application specific integrated circuit, as well as a method of testing such a circuit, are disclosed herein. In one example embodiment, the integrated circuit includes a plurality of pins including a power pin, a ground pin, and a first communication pin, a test mode circuit, and a communication circuit. The integrated circuit additionally includes a first switch connected to the first communication pin, where the first switch is configured to couple the first communication pin to either the test mode circuit or the communication circuit. The integrated circuit further includes a control circuit coupled to the first switch and configured to control whether the first switch is operated to couple the first communication pin to the test mode circuit or to the communication circuit based upon or in response to an operating mode.

Abstract: An integrated circuit, such as for example an application specific integrated circuit, as well as a method of testing such a circuit, are disclosed herein. In one example embodiment, the integrated circuit includes a plurality of pins including a power pin, a ground pin, and a first communication pin, a test mode circuit, and a communication circuit. The integrated circuit additionally includes a first switch connected to the first communication pin, where the first switch is configured to couple the first communication pin to either the test mode circuit or the communication circuit. The integrated circuit further includes a control circuit coupled to the first switch and configured to control whether the first switch is operated to couple the first communication pin to the test mode circuit or to the communication circuit based upon or in response to an operating mode.