Patents by Inventor Divya Subbarao Anvekar

Divya Subbarao Anvekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for testing a large memory area during processor design verification and validation
    Patent number: 7992059
    Abstract: A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test case set (multiple test cases) along with an initial address translation buffer that includes real addresses that reference an initial memory block. A test case executor modifies the real addresses after each test case set re-execution in order for a processor to test each replicated memory block included in the main memory.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: Divya Subbarao Anvekar, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor
  • System and Method for Testing a Large Memory Area During Processor Design Verification and Validation
    Publication number: 20090070643
    Abstract: A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test case set (multiple test cases) along with an initial address translation buffer that includes real addresses that reference an initial memory block. A test case executor modifies the real addresses after each test case set re-execution in order for a processor to test each replicated memory block included in the main memory.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Inventors: Divya Subbarao Anvekar, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor