Patents by Inventor Divya Tripathi

Divya Tripathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294359
    Abstract: An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: May 6, 2025
    Assignee: NXP B.V.
    Inventors: Sanjay Kumar Wadhwa, Divya Tripathi, Saurabh Goyal, Alvin Leng Sun Loke, Manish Kumar Upadhyay
  • Patent number: 12249957
    Abstract: A self-biased, closed loop, low current free running oscillator clock generator method and apparatus are provided with a current mode comparator connected to a trimming resistor and configured to compare an internally generated voltage reference VREF signal to a voltage feedback signal VFB, where the current mode comparator comprises a common gate amplifier connected to a current mirror circuit in a negative self-biased closed loop to generate a control current signal for controlling a current controlled oscillator to produce an output clock signal having a clock frequency based on the control current signal, where a frequency-to-voltage converter is connected in a feedback path to receive the output clock signal and is configured to produce the voltage feedback signal VFB for input to the current mode comparator, wherein the clock frequency of the output clock signal is tuned to a nominal locked output frequency fOUT by the trimming resistor.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: March 11, 2025
    Assignee: NXP USA, Inc.
    Inventors: Divya Tripathi, Sadique Mohammad Iqbal, Anubhav Srivastava, Krishna Thakur, Pragya Priya Malakar, John Pigott
  • Patent number: 12191859
    Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: January 7, 2025
    Assignee: NXP B.V.
    Inventors: Saurabh Goyal, Divya Tripathi, Krishna Thakur, Deependra Kumar Jain
  • Publication number: 20240388252
    Abstract: Systems and methods for providing temperature compensation in oscillators circuits are discussed. In various embodiments, these systems and methods may be implemented in technologies where only resistors with the same type (positive or negative) of temperature coefficients of resistance are available. For example, in some implementations, an oscillator circuit may include a voltage generator coupled to an input terminal of a common gate amplifier through a first resistor, and a frequency-to-voltage converter coupled to another input terminal of the common gate amplifier through a second resistor, where the second resistor may be configured to reduce a frequency variation of the oscillator circuit in response to temperature changes.
    Type: Application
    Filed: November 14, 2023
    Publication date: November 21, 2024
    Inventors: Sadique Mohammad Iqbal, Divya Tripathi, Anubhav Srivastava, Krishna Thakur
  • Publication number: 20240204757
    Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.
    Type: Application
    Filed: June 9, 2023
    Publication date: June 20, 2024
    Inventors: Saurabh Goyal, Divya Tripathi, Krishna Thakur, Deependra Kumar Jain
  • Publication number: 20240178858
    Abstract: A low current, adaptively-biased switched resistor digital-to-analog converter (RDAC) circuit, method and apparatus are provided with a coarse trim ladder and a fine trim ladder connected with a plurality of NFET switches to generate an output reference voltage from an input supply voltage, where the bulk semiconductor substrate regions for the NFET switches in at least the fine trim ladder are driven by a unity gain buffer which is connected in feedback to receive the output reference voltage and to generate a buffered reference voltage which is directly connected to bulk semiconductor regions of the NFET switches, thereby providing a low current, low circuit area solution with reduced leakage current and temperature variation.
    Type: Application
    Filed: May 11, 2023
    Publication date: May 30, 2024
    Inventors: Saurabh Goyal, Krishna Thakur, Divya Tripathi, Deependra Kumar Jain
  • Publication number: 20240113660
    Abstract: A self-biased, closed loop, low current free running oscillator clock generator method and apparatus are provided with a current mode comparator connected to a trimming resistor and configured to compare an internally generated voltage reference VREF signal to a voltage feedback signal VFB, where the current mode comparator comprises a common gate amplifier connected to a current mirror circuit in a negative self-biased closed loop to generate a control current signal for controlling a current controlled oscillator to produce an output clock signal having a clock frequency based on the control current signal, where a frequency-to-voltage converter is connected in a feedback path to receive the output clock signal and is configured to produce the voltage feedback signal VFB for input to the current mode comparator, wherein the clock frequency of the output clock signal is tuned to a nominal locked output frequency fOUT by the trimming resistor.
    Type: Application
    Filed: April 6, 2023
    Publication date: April 4, 2024
    Inventors: Divya Tripathi, Sadique Mohammad Iqbal, Anubhav Srivastava, Krishna Thakur
  • Publication number: 20230361772
    Abstract: An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 9, 2023
    Inventors: Sanjay Kumar Wadhwa, Divya Tripathi, Saurabh Goyal, Alvin Leng Sun Loke, Manish Kumar Upadhyay
  • Patent number: 11581878
    Abstract: A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: February 14, 2023
    Assignee: NXP B.V.
    Inventors: Sanjay Kumar Wadhwa, Saurabh Goyal, Divya Tripathi
  • Patent number: 11378991
    Abstract: A soft-start circuit for a voltage regulator includes a comparator and a delay circuit. The comparator compares an output voltage, that is generated by the voltage regulator, and a reference voltage to generate a comparison signal. Further, the delay circuit receives the reference voltage and a control signal that is outputted based on the comparison signal, and outputs and provides another reference voltage to the voltage regulator. During a start-up of the voltage regulator, the reference voltage outputted by the delay circuit is a delayed version of the reference voltage received by the delay circuit. Thus, the soft-start circuit mitigates an overshoot of the output voltage during the start-up. Further, on completion of the start-up, the reference voltage outputted by the delay circuit is equal to the reference voltage received by the delay circuit.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 5, 2022
    Assignee: NXP B.V.
    Inventors: Saurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi
  • Patent number: 11277121
    Abstract: A level shifter includes a pull-down circuit, a pull-up circuit, a protection circuit, and an output generator. The pull-down circuit is configured to receive input voltages, and generate bias voltages. The input voltages are associated with a voltage domain. The pull-up circuit is configured to receive a supply voltage and generate control voltages. The protection circuit is configured to receive reference voltages, and control the generation of the bias voltages and the control voltages. The output generator is configured to receive at least one of the reference voltages, and at least one of the bias voltages and the control voltages, and generate output voltages that are able to reach minimum and maximum voltage levels of another voltage domain. Further, the output voltages remain unaffected by variations in process, voltage, and temperature.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: March 15, 2022
    Assignee: NXP B.V.
    Inventors: Saurabh Goyal, Divya Tripathi, Sanjay Kumar Wadhwa
  • Patent number: 10447246
    Abstract: A low voltage differential signaling circuit includes an output driver circuit configured to provide a differential signal pair based on a first signal and a second signal. A peak detect circuit is coupled to receive the differential signal pair and configured to provide a feedback signal based on the differential signal pair and the first and second signals. An amplifier circuit has a first input coupled to the peak detect circuit, a second input coupled to receive a reference voltage, and an output coupled to provide a bias voltage to the output driver circuit.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 15, 2019
    Assignee: NXP USA, INC.
    Inventors: Divya Tripathi, Anil Kumar Gottapu, Sanjay Kumar Wadhwa
  • Patent number: 9654096
    Abstract: A power-on-reset (POR) circuit for a system-on-chip (SOC) includes a biased switching element having a source, drain, and gate, with the source being connected to a supply voltage and the drain and gate being connected to a control line. The POR circuit further includes a first delay switching element having a source connected to a reduced supply voltage, a gate connected to the control line, and a drain, and an inverter having an input and an output, with the input being connected to the drain of the first delay switching element. The inverter includes a first CMOS inverter coupled between the supply voltage and a reference voltage. A first capacitor is coupled between the inverter input and the reference voltage. A second capacitor coupled between the inverter input and an output of the first CMOS inverter.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: May 16, 2017
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Sanjay K. Wadhwa, Divya Tripathi
  • Publication number: 20160187900
    Abstract: A voltage regulator circuit with two series connected resistors connected together at a common resistor node. An initial conducting path has a first pass transistor with a first terminal connected to a first supply rail and a second terminal connected to a regulated output voltage. A main conducting path has a second pass transistor with a first terminal connected to the first supply rail and a second terminal connected to the regulated output voltage. A comparator has an input connected to the common resistor node output is connected to a gate of the first pass transistor. A voltage threshold switch is connected to the common resistor node, and based on the voltage at the common resistor node the voltage threshold switch selectively connects a gate of the second pass transistor to the comparator output.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: Kailash Dhiman, Nidhi Chaudhry, Divya Tripathi
  • Patent number: 9229465
    Abstract: A current-starved inverter circuit includes first and second current-mirror circuits, first and second transistors, a detector, and a current-booster. The first and second transistors receive a first source current and a first sink current from the first and second current-mirror circuits, respectively, and an input voltage signal, and generate an inverted input voltage signal (an output voltage signal). The detector generates a first detection signal when the output voltage signal exceeds a first threshold value and a second detection signal when the output voltage signal is less than a second threshold value. The current-booster, which is connected to the detector, receives the first and second detection signals and provides a second source current and a second sink current to the first and second transistors to pull-up and pull-down a voltage level of the output voltage signal, respectively.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: January 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Kailash Dhiman, Parul Sharma, Divya Tripathi
  • Publication number: 20150277462
    Abstract: A current-starved inverter circuit includes first and second current-mirror circuits, first and second transistors, a detector, and a current-booster. The first and second transistors receive a first source current and a first sink current from the first and second current-mirror circuits, respectively, and an input voltage signal, and generate an inverted input voltage signal (an output voltage signal). The detector generates a first detection signal when the output voltage signal exceeds a first threshold value and a second detection signal when the output voltage signal is less than a second threshold value. The current-booster, which is connected to the detector, receives the first and second detection signals and provides a second source current and a second sink current to the first and second transistors to pull-up and pull-down a voltage level of the output voltage signal, respectively.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Inventors: Kailash Dhiman, Parul Sharma, Divya Tripathi
  • Patent number: 7495465
    Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Qadeer A. Khan, Sanjay K Wadhwa, Divya Tripathi, Siddhartha Gk, Kulbhushan Misri
  • Patent number: 7446592
    Abstract: A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: November 4, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Divya Tripathi, Siddhartha Gk, Qadeer A. Khan, Kulbhushan Misri, Sanjay K Wadhwa
  • Patent number: 7414462
    Abstract: A differential receiver circuit receives a differential input signal including first and second input signals (DP, DM) and generates a single-ended output signal. The receiver circuit includes first and second comparators that receive the differential input signal and generate respective first and second differential output signals. A current summer is connected to the first and second comparators and receives the first and second differential output signals and generates a third differential output signal. A differential to single-ended converter is connected to the current summer and receives the third differential output signal and generates the single-ended output signal. The differential input signal varies from a ground voltage level to an external reference voltage level (VUSB), while the first and second comparators are made with devices that operate at an internal reference voltage level that is lower than the external reference voltage level.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: August 19, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Divya Tripathi, Jaideep Banerjee, Qadeer A. Khan
  • Patent number: 7388419
    Abstract: A compensation circuit and a method for compensating for process, voltage and temperature (PVT) variations in an integrated circuit (IC). The IC includes several functional modules, each of which includes a set of functional units, and generates an output signal in response to an input signal. The compensation circuit includes a code generator and a logic module. The code generator generates a digital code for each functional unit. The digital codes are based on phase differences between the input signal and the output signal. The logic module generates calibration codes based on the digital codes. The calibration codes compensate for the PVT variations in the corresponding functional units.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: June 17, 2008
    Assignee: Freescale Semiconductor, Inc
    Inventors: Siddhartha Gk, Qadeer A. Khan, Divya Tripathi, Sanjay K Wadhwa, Kulbhushan Misri