Patents by Inventor Divya Tripathi
Divya Tripathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113660Abstract: A self-biased, closed loop, low current free running oscillator clock generator method and apparatus are provided with a current mode comparator connected to a trimming resistor and configured to compare an internally generated voltage reference VREF signal to a voltage feedback signal VFB, where the current mode comparator comprises a common gate amplifier connected to a current mirror circuit in a negative self-biased closed loop to generate a control current signal for controlling a current controlled oscillator to produce an output clock signal having a clock frequency based on the control current signal, where a frequency-to-voltage converter is connected in a feedback path to receive the output clock signal and is configured to produce the voltage feedback signal VFB for input to the current mode comparator, wherein the clock frequency of the output clock signal is tuned to a nominal locked output frequency fOUT by the trimming resistor.Type: ApplicationFiled: April 6, 2023Publication date: April 4, 2024Inventors: Divya Tripathi, Sadique Mohammad Iqbal, Anubhav Srivastava, Krishna Thakur
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Publication number: 20230361772Abstract: An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.Type: ApplicationFiled: May 5, 2022Publication date: November 9, 2023Inventors: Sanjay Kumar Wadhwa, Divya Tripathi, Saurabh Goyal, Alvin Leng Sun Loke, Manish Kumar Upadhyay
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Patent number: 11581878Abstract: A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.Type: GrantFiled: October 8, 2021Date of Patent: February 14, 2023Assignee: NXP B.V.Inventors: Sanjay Kumar Wadhwa, Saurabh Goyal, Divya Tripathi
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Patent number: 11378991Abstract: A soft-start circuit for a voltage regulator includes a comparator and a delay circuit. The comparator compares an output voltage, that is generated by the voltage regulator, and a reference voltage to generate a comparison signal. Further, the delay circuit receives the reference voltage and a control signal that is outputted based on the comparison signal, and outputs and provides another reference voltage to the voltage regulator. During a start-up of the voltage regulator, the reference voltage outputted by the delay circuit is a delayed version of the reference voltage received by the delay circuit. Thus, the soft-start circuit mitigates an overshoot of the output voltage during the start-up. Further, on completion of the start-up, the reference voltage outputted by the delay circuit is equal to the reference voltage received by the delay circuit.Type: GrantFiled: June 23, 2021Date of Patent: July 5, 2022Assignee: NXP B.V.Inventors: Saurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi
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Patent number: 11277121Abstract: A level shifter includes a pull-down circuit, a pull-up circuit, a protection circuit, and an output generator. The pull-down circuit is configured to receive input voltages, and generate bias voltages. The input voltages are associated with a voltage domain. The pull-up circuit is configured to receive a supply voltage and generate control voltages. The protection circuit is configured to receive reference voltages, and control the generation of the bias voltages and the control voltages. The output generator is configured to receive at least one of the reference voltages, and at least one of the bias voltages and the control voltages, and generate output voltages that are able to reach minimum and maximum voltage levels of another voltage domain. Further, the output voltages remain unaffected by variations in process, voltage, and temperature.Type: GrantFiled: January 28, 2021Date of Patent: March 15, 2022Assignee: NXP B.V.Inventors: Saurabh Goyal, Divya Tripathi, Sanjay Kumar Wadhwa
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Patent number: 10447246Abstract: A low voltage differential signaling circuit includes an output driver circuit configured to provide a differential signal pair based on a first signal and a second signal. A peak detect circuit is coupled to receive the differential signal pair and configured to provide a feedback signal based on the differential signal pair and the first and second signals. An amplifier circuit has a first input coupled to the peak detect circuit, a second input coupled to receive a reference voltage, and an output coupled to provide a bias voltage to the output driver circuit.Type: GrantFiled: November 6, 2018Date of Patent: October 15, 2019Assignee: NXP USA, INC.Inventors: Divya Tripathi, Anil Kumar Gottapu, Sanjay Kumar Wadhwa
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Patent number: 9654096Abstract: A power-on-reset (POR) circuit for a system-on-chip (SOC) includes a biased switching element having a source, drain, and gate, with the source being connected to a supply voltage and the drain and gate being connected to a control line. The POR circuit further includes a first delay switching element having a source connected to a reduced supply voltage, a gate connected to the control line, and a drain, and an inverter having an input and an output, with the input being connected to the drain of the first delay switching element. The inverter includes a first CMOS inverter coupled between the supply voltage and a reference voltage. A first capacitor is coupled between the inverter input and the reference voltage. A second capacitor coupled between the inverter input and an output of the first CMOS inverter.Type: GrantFiled: July 19, 2016Date of Patent: May 16, 2017Assignee: FREESCALE SEMICONDUCTOR,INC.Inventors: Sanjay K. Wadhwa, Divya Tripathi
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Publication number: 20160187900Abstract: A voltage regulator circuit with two series connected resistors connected together at a common resistor node. An initial conducting path has a first pass transistor with a first terminal connected to a first supply rail and a second terminal connected to a regulated output voltage. A main conducting path has a second pass transistor with a first terminal connected to the first supply rail and a second terminal connected to the regulated output voltage. A comparator has an input connected to the common resistor node output is connected to a gate of the first pass transistor. A voltage threshold switch is connected to the common resistor node, and based on the voltage at the common resistor node the voltage threshold switch selectively connects a gate of the second pass transistor to the comparator output.Type: ApplicationFiled: December 24, 2014Publication date: June 30, 2016Inventors: Kailash Dhiman, Nidhi Chaudhry, Divya Tripathi
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Patent number: 9229465Abstract: A current-starved inverter circuit includes first and second current-mirror circuits, first and second transistors, a detector, and a current-booster. The first and second transistors receive a first source current and a first sink current from the first and second current-mirror circuits, respectively, and an input voltage signal, and generate an inverted input voltage signal (an output voltage signal). The detector generates a first detection signal when the output voltage signal exceeds a first threshold value and a second detection signal when the output voltage signal is less than a second threshold value. The current-booster, which is connected to the detector, receives the first and second detection signals and provides a second source current and a second sink current to the first and second transistors to pull-up and pull-down a voltage level of the output voltage signal, respectively.Type: GrantFiled: March 26, 2014Date of Patent: January 5, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Kailash Dhiman, Parul Sharma, Divya Tripathi
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Publication number: 20150277462Abstract: A current-starved inverter circuit includes first and second current-mirror circuits, first and second transistors, a detector, and a current-booster. The first and second transistors receive a first source current and a first sink current from the first and second current-mirror circuits, respectively, and an input voltage signal, and generate an inverted input voltage signal (an output voltage signal). The detector generates a first detection signal when the output voltage signal exceeds a first threshold value and a second detection signal when the output voltage signal is less than a second threshold value. The current-booster, which is connected to the detector, receives the first and second detection signals and provides a second source current and a second sink current to the first and second transistors to pull-up and pull-down a voltage level of the output voltage signal, respectively.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Inventors: Kailash Dhiman, Parul Sharma, Divya Tripathi
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Patent number: 7495465Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.Type: GrantFiled: July 20, 2006Date of Patent: February 24, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Khan, Sanjay K Wadhwa, Divya Tripathi, Siddhartha Gk, Kulbhushan Misri
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Patent number: 7446592Abstract: A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.Type: GrantFiled: July 20, 2006Date of Patent: November 4, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Divya Tripathi, Siddhartha Gk, Qadeer A. Khan, Kulbhushan Misri, Sanjay K Wadhwa
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Patent number: 7414462Abstract: A differential receiver circuit receives a differential input signal including first and second input signals (DP, DM) and generates a single-ended output signal. The receiver circuit includes first and second comparators that receive the differential input signal and generate respective first and second differential output signals. A current summer is connected to the first and second comparators and receives the first and second differential output signals and generates a third differential output signal. A differential to single-ended converter is connected to the current summer and receives the third differential output signal and generates the single-ended output signal. The differential input signal varies from a ground voltage level to an external reference voltage level (VUSB), while the first and second comparators are made with devices that operate at an internal reference voltage level that is lower than the external reference voltage level.Type: GrantFiled: May 30, 2006Date of Patent: August 19, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Divya Tripathi, Jaideep Banerjee, Qadeer A. Khan
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Patent number: 7388419Abstract: A compensation circuit and a method for compensating for process, voltage and temperature (PVT) variations in an integrated circuit (IC). The IC includes several functional modules, each of which includes a set of functional units, and generates an output signal in response to an input signal. The compensation circuit includes a code generator and a logic module. The code generator generates a digital code for each functional unit. The digital codes are based on phase differences between the input signal and the output signal. The logic module generates calibration codes based on the digital codes. The calibration codes compensate for the PVT variations in the corresponding functional units.Type: GrantFiled: July 20, 2006Date of Patent: June 17, 2008Assignee: Freescale Semiconductor, IncInventors: Siddhartha Gk, Qadeer A. Khan, Divya Tripathi, Sanjay K Wadhwa, Kulbhushan Misri
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Publication number: 20070279125Abstract: A differential receiver circuit receives a differential input signal including first and second input signals (DP, DM) and generates a single-ended output signal. The receiver circuit includes first and second comparators that receive the differential input signal and generate respective first and second differential output signals. A current summer is connected to the first and second comparators and receives the first and second differential output signals and generates a third differential output signal. A differential to single-ended converter is connected to the current summer and receives the third differential output signal and generates the single-ended output signal. The differential input signal varies from a ground voltage level to an external reference voltage level (VUSB), while the first and second comparators are made with devices that operate at an internal reference voltage level that is lower than the external reference voltage level.Type: ApplicationFiled: May 30, 2006Publication date: December 6, 2007Inventors: Divya Tripathi, Jaideep Banerjee, Qadeer A. Khan
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Patent number: 7292073Abstract: A transmission line driver circuit that operates at a first voltage level is fabricated using devices that operate at a second, lower voltage level. The driver circuit includes a ramp generator that receives a speed signal and a data signal and generates a charge ramp signal and a discharge ramp signal. A pair of series connected source follower transistors have their gates connected to respective charge and discharge signal outputs of the ramp generator. The driver circuit output signal is generated at an output node between the sources of the NMOS and PMOS source follower transistors. A charge_ls generator circuit provides a charge_ls signal and a discharge_ls generator circuit provides a discharge_ls signal. A pair of protection transistors includes a first NMOS protection transistor and a first PMOS protection transistor, which are connected in series with respective ones of the source follower transistors, and their gates are connected to respective ones of the charge and discharge signals.Type: GrantFiled: May 30, 2006Date of Patent: November 6, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Khan, Divya Tripathi
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Patent number: 7187197Abstract: A transmission line driver with slew rate control includes high and low side ramp generators for generating charge and discharge ramp signals, respectively, which are input to respective comparators and a pair of source follower transistors. A pair of additional transistors is connected to the pair of source follower transistors and a pair of staggered drivers is connected to the pair of additional transistors.Type: GrantFiled: April 4, 2005Date of Patent: March 6, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Divya Tripathi, Qadeer A. Khan, Kulbhushan Misri
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Publication number: 20070018713Abstract: A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.Type: ApplicationFiled: July 20, 2006Publication date: January 25, 2007Inventors: Divya Tripathi, Siddhartha Gk, Qadeer Khan, Kulbhushan Misri, Sanjay Wadhwa
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Publication number: 20070018864Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.Type: ApplicationFiled: July 20, 2006Publication date: January 25, 2007Inventors: Qadeer Khan, Sanjay Wadhwa, Divya Tripathi, Siddhartha Gk, Kulbhushan Misri
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Publication number: 20070018712Abstract: A compensation circuit and a method for compensating for process, voltage and temperature (PVT) variations in an integrated circuit (IC). The IC includes several functional modules, each of which includes a set of functional units, and generates an output signal in response to an input signal. The compensation circuit includes a code generator and a logic module. The code generator generates a digital code for each functional unit. The digital codes are based on phase differences between the input signal and the output signal. The logic module generates calibration codes based on the digital codes. The calibration codes compensate for the PVT variations in the corresponding functional units.Type: ApplicationFiled: July 20, 2006Publication date: January 25, 2007Inventors: Siddhartha GK, Qadeer Khan, Divya Tripathi, Sanjay Wadhwa, Kulbhushan Misri