Patents by Inventor Divyank Gupta

Divyank Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240037457
    Abstract: Embodiments detect data drift associated with machine learning (“ML”) models. Embodiments identify a first feature stored by a feature store, where the feature store includes an offline store and an online store. Embodiments determine one or more first trained ML models that are using the first feature. For each of the first trained ML models, embodiments invoke the first trained ML model using synthetic data or validation data, generate metrics to determine an accuracy of the first trained ML model and, when the accuracy is below a threshold, generate an alert notifying of a first data drift for the first trained ML model.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Dwijen BHATTACHARJEE, Hari Bhaskar SANKARANARAYANAN, Divyank GUPTA
  • Publication number: 20210311729
    Abstract: Systems and methods provide acquisition of a plurality of code artifacts and one or more code review comments associated with each code artifact, generation of a set of code features based on each of the plurality of code artifacts, input of each set of code features to a neural network to generate code review comments respectively associated with each of the plurality of code artifacts, determination of a loss by comparing each generated code review comment respectively associated with one of plurality of code artifacts with the one or more review comments associated with the one of plurality of code artifacts, and modification of the neural network based on the loss.
    Type: Application
    Filed: May 18, 2020
    Publication date: October 7, 2021
    Inventors: Divyank Gupta, Shaswat Deep
  • Publication number: 20190066769
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to a dummy wordline load via a dummy wordline. The integrated circuit may include underdrive circuitry coupled to the dummy wordline between the dummy wordline driver and the dummy wordline load. The underdrive circuitry may generate an underdrive on the dummy wordline when the dummy wordline is selected and driven by the dummy wordline driver.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Inventors: Vivek Asthana, Nitin Jindal, Nikhil Kaushik, Kapil Mittal, Divyank Gupta, Shakir Malik, Stefi Bhavsar
  • Patent number: 10217506
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to a dummy wordline load via a dummy wordline. The integrated circuit may include underdrive circuitry coupled to the dummy wordline between the dummy wordline driver and the dummy wordline load. The underdrive circuitry may generate an underdrive on the dummy wordline when the dummy wordline is selected and driven by the dummy wordline driver.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: February 26, 2019
    Assignee: ARM Limited
    Inventors: Vivek Asthana, Nitin Jindal, Nikhil Kaushik, Kapil Mittal, Divyank Gupta, Shakir Malik, Stefi Bhavsar