Patents by Inventor Divyeshkumar Mahendrabhai PATEL

Divyeshkumar Mahendrabhai PATEL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387975
    Abstract: Examples of this description provide for a method. In some examples, the method includes determining, via a circuit, an estimated value of harmonic coupling in a transmitted signal via a feedback signal path that receives the transmitted signal and performing pre-compensation for the harmonic coupling based on the estimated value, the pre-compensation performed in the circuit.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Sarma Sundareswara GUNTURI, Divyeshkumar Mahendrabhai PATEL, Sai Vaibhav BATCHU, Divyansh Deepak JAIN, Aswath VS
  • Publication number: 20220182098
    Abstract: A technique for reinitializing a coupled circuit, the technique including receiving a common configuration value associated with states of a coupled circuit, tracking states associated with the coupled circuit while the coupled circuit is in a low power state based on the common configuration value, receiving the tracked state associated with the coupled circuit, receiving a scaling value associated with the coupled circuit, determining a current state of the coupled circuit based on the tracked state and the scaling value, and transmitting an indication of the current state to the coupled circuit when the coupled circuit has exited the low power state.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 9, 2022
    Inventors: Sundarrajan RANGACHARI, Nagalinga Swamy Basayya AREMALLAPUR, Kalyan GUDIPATI, Divyeshkumar Mahendrabhai PATEL, Venkateshwara Reddy POTHAPU, Aravind VIJAYAKUMAR, Sarma Sundareswara GUNTURI, Jaiganesh BALAKRISHNAN
  • Patent number: 11239854
    Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jawaharlal Tangudu, Pankaj Gupta, Sreenath Narayanan Potty, Ajai Paulose, Chandrasekhar Sriram, Mahesh Ravi Varma, Shabbar Abbasi Vejlani, Neeraj Shrivastava, Himanshu Varshney, Divyeshkumar Mahendrabhai Patel, Raju Kharataram Chaudhari
  • Publication number: 20210105021
    Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.
    Type: Application
    Filed: October 2, 2020
    Publication date: April 8, 2021
    Inventors: Jawaharlal TANGUDU, Pankaj GUPTA, Sreenath Narayanan POTTY, Ajai PAULOSE, Chandrasekhar SRIRAM, Mahesh Ravi VARMA, Shabbar Abbasi VEJLANI, Neeraj SHRIVASTAVA, Himanshu VARSHNEY, Divyeshkumar Mahendrabhai PATEL, Raju Kharataram CHAUDHARI