Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon as-deposited may be characterized by less than or about 3% hydrogen incorporation.

Abstract: A target concentration profile for a film to be deposited on a surface of a substrate during a deposition process for the substrate at a process chamber of a manufacturing system is identified. Data of the target concentration profile is processed using a model. The model outputs a set of deposition process settings that corresponds to the target concentration profile. One or more operations of the deposition process are performed in accordance with the set of deposition process settings.

Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the boron-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the silicon-containing precursor or the boron-containing precursor is greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber.

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

Abstract: Exemplary semiconductor processing systems may include an inductively coupled plasma source. The systems may include an RF power source that is electrically coupled with the inductively coupled plasma source. The systems may include a first gas source fluidly coupled with the inductively coupled plasma source. The systems may include a second gas source. The systems may include a dual-channel showerhead assembly defining a first plurality of apertures and a second plurality of apertures. The first plurality of apertures may be fluidly coupled with the inductively coupled plasma source. The second plurality of apertures are fluidly coupled with the second gas source.

Abstract: Methods and apparatus for surface profiling and texturing of chamber components for use in a process chamber, such surface-profiled or textured chamber components, and method of use of same are provided herein. In some embodiments, a method includes measuring a parameter of a reference substrate or a heated pedestal using one or more sensors and modifying a surface of a chamber component physically based on the measured parameter.

Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by less than or about 3% hydrogen incorporation.

Abstract: Methods and systems for controlling concentration profiles of deposited films using machine learning are provided. Data associated with a target concentration profile for a film to be deposited on a surface of a substrate during a deposition process for the substrate is provided as input to a trained machine learning model. One or more outputs of the trained machine learning model are obtained. Process recipe data identifying one or more sets of deposition process settings is determined from the one or more outputs. For each set of deposition process setting, an indication of a level of confidence that a respective set of deposition process settings corresponds to the target concentration profile for the film to be deposited on the substrate is also determined.

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

Abstract: Exemplary substrate support assemblies include an electrostatic chuck body defining a substrate platform. The substrate platform may be characterized by an upper surface. The platform may define a purge aperture. The platform may include a plurality of mesas that are disposed in an inner region of the upper surface. Each of the mesas may protrude upward from the upper surface. The platform may include a sealing band that extends upward from the upper surface in a circumferential pattern and partially encircles the inner region of the upper surface. Top surfaces of the mesas and sealing band may form a support surface for a substrate. The sealing band may define a number of gaps. The assemblies may include a support stem coupled with the electrostatic chuck body, a heater embedded within the electrostatic chuck body, and a backside gas source that is coupled with the purge aperture of the support surface.

Abstract: Methods and systems for controlling concentration profiles of deposited films using machine learning are provided. Data associated with a target concentration profile for a film to be deposited on a surface of a substrate during a deposition process for the substrate is provided as input to a trained machine learning model. One or more outputs of the trained machine learning model are obtained. Process recipe data identifying one or more sets of deposition process settings is determined from the one or more outputs. For each set of deposition process setting, an indication of a level of confidence that a respective set of deposition process settings corresponds to the target concentration profile for the film to be deposited on the substrate is also determined.

Abstract: Exemplary methods of semiconductor processing may include forming a plasma of a fluorine-containing precursor. The methods may include performing a chamber clean in a processing region of a semiconductor processing chamber. The processing region may be at least partially defined between a faceplate and a substrate support. The methods may include generating aluminum fluoride during the chamber clean. The methods may include contacting surfaces within the processing region with a carbon-containing precursor. The methods may include volatilizing aluminum fluoride from the surfaces of the processing region.

Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.

Abstract: Exemplary substrate support assemblies include an electrostatic chuck body defining a substrate platform. The substrate platform may be characterized by an upper surface. The platform may define a purge aperture. The platform may include a plurality of mesas that are disposed in an inner region of the upper surface. Each of the mesas may protrude upward from the upper surface. The platform may include a sealing band that extends upward from the upper surface in a circumferential pattern and partially encircles the inner region of the upper surface. Top surfaces of the mesas and sealing band may form a support surface for a substrate. The sealing band may define a number of gaps. The assemblies may include a support stem coupled with the electrostatic chuck body, a heater embedded within the electrostatic chuck body, and a backside gas source that is coupled with the purge aperture of the support surface.

Abstract: Semiconductor processing systems according to embodiments of the present technology may include a chamber body having sidewalls and a base. The chamber body may define an internal volume. The systems may include a substrate support assembly having a shaft and a platen coupled with the shaft along a first surface of the platen. The semiconductor processing systems may include a cover plate positioned on the platen of the substrate support assembly along a second surface of the platen opposite the first surface. The cover plate may include a flange extending about an exterior region of the cover plate. The flange may be in direct contact with the platen. The cover plate may include an upper wall vertically offset from the flange. An interior volume may be defined between the upper wall and the platen of the substrate support assembly.

Abstract: A semiconductor processing system includes a remote plasma source (RPS), a faceplate, and an output manifold positioned between the RPS and the faceplate. The output manifold is characterized by a plurality of purge outlets that are fluidly coupled with a purge gas source and a plurality of deposition outlets that are fluidly coupled with a deposition gas source. A delivery tube extends between and fluidly couples the RPS and the faceplate. The delivery tube is characterized by a generally cylindrical sidewall that defines an upper plurality of apertures that are arranged in a radial pattern. Each of the upper apertures is fluidly coupled with one of the purge outlets. The generally cylindrical sidewall defines a lower plurality of apertures that are arranged in a radial pattern and below the upper plurality of apertures. Each of the lower apertures is fluidly coupled with one of the deposition outlets.

Abstract: Exemplary semiconductor processing chambers may include a faceplate assembly characterized by at least one surface defining a number of voids. Each void is configured to receive an interchangeable thermal body that can be selected from multiple interchangeable thermal bodies. Exemplary semiconductor processing chambers may also include a gas box characterized by movable members. Each movable member is configured to engage a delivery port and is movable to provide flow control for a gas being delivered to the processing volume through a gas flow path. Zoned flow and/or temperature control may be provided by the faceplate assembly, the gas box, or both.

Abstract: Exemplary semiconductor processing systems may include a chamber body comprising sidewalls and a base. The systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate defining a plurality of channels through an interior of the support plate. Each channel of the plurality of channels may include a radial portion extending outward from a central channel through the support plate. Each channel may also include a vertical portion formed at an exterior region of the support plate fluidly coupling the radial portion with a support surface of the support plate. The substrate support may include a shaft coupled with the support plate. The central channel may extend through the shaft. The systems may include a fluid source coupled with the central channel of the substrate support.

Abstract: Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H2) into the substrate processing region of the semiconductor processing chamber. The boron-containing precursor and the H2 may be flowed at a boron-to-hydrogen flow rate ratio. The flow rate of the boron-containing precursor and the H2 may be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. The boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.