Patents by Inventor Diwakar Kedlaya

Diwakar Kedlaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961739
    Abstract: Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H2) into the substrate processing region of the semiconductor processing chamber. The boron-containing precursor and the H2 may be flowed at a boron-to-hydrogen flow rate ratio. The flow rate of the boron-containing precursor and the H2 may be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. The boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 16, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yi Yang, Krishna Nittala, Rui Cheng, Karthik Janakiraman, Diwakar Kedlaya, Zubin Huang, Aykut Aydin
  • Patent number: 11939674
    Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the boron-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the silicon-containing precursor or the boron-containing precursor is greater than or about 1:1. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: March 26, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yi Yang, Krishna Nittala, Karthik Janakiraman, Aykut Aydin, Diwakar Kedlaya
  • Publication number: 20240079220
    Abstract: Semiconductor processing systems and methods are disclosed. An exemplary semiconductor processing system may include a semiconductor processing chamber containing a solid boron deposit, a remote plasma unit disposed upstream of the semiconductor processing chamber, and an optical absorption sensor disposed downstream of the semiconductor processing chamber. The remote plasma unit may be configured to generate plasma effluents from a fluorine-containing precursor. The optical absorption sensor may be configured to measure within an outflow from the semiconductor processing chamber a level of a boron-containing compound produced via a reaction between at least a portion of the solid boron deposit and the plasma effluents flowed from the remote plasma unit into the semiconductor processing chamber.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 7, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Fang Ruan, Diwakar Kedlaya
  • Patent number: 11862475
    Abstract: A semiconductor processing system includes a remote plasma source (RPS), a faceplate, and an output manifold positioned between the RPS and the faceplate. The output manifold is characterized by a plurality of purge outlets that are fluidly coupled with a purge gas source and a plurality of deposition outlets that are fluidly coupled with a deposition gas source. A delivery tube extends between and fluidly couples the RPS and the faceplate. The delivery tube is characterized by a generally cylindrical sidewall that defines an upper plurality of apertures that are arranged in a radial pattern. Each of the upper apertures is fluidly coupled with one of the purge outlets. The generally cylindrical sidewall defines a lower plurality of apertures that are arranged in a radial pattern and below the upper plurality of apertures. Each of the lower apertures is fluidly coupled with one of the deposition outlets.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: January 2, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Fang Ruan, Diwakar Kedlaya, Amit Bansal, Venkata Sharat Chandra Parimi, Rajaram Narayanan, Badri N. Ramamurthi, Sherry L. Mings, Job George Konnoth Joseph, Rupankar Choudhury
  • Patent number: 11848178
    Abstract: Semiconductor processing systems and methods are disclosed. An exemplary semiconductor processing system may include a semiconductor processing chamber containing a solid boron deposit, a remote plasma unit disposed upstream of the semiconductor processing chamber, and an optical absorption sensor disposed downstream of the semiconductor processing chamber. The remote plasma unit may be configured to generate plasma effluents from a fluorine-containing precursor. The optical absorption sensor may be configured to measure within an outflow from the semiconductor processing chamber a level of a boron-containing compound produced via a reaction between at least a portion of the solid boron deposit and the plasma effluents flowed from the remote plasma unit into the semiconductor processing chamber.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 19, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Fang Ruan, Diwakar Kedlaya
  • Publication number: 20230390811
    Abstract: Exemplary semiconductor processing systems may include a processing chamber defining a processing region. The systems may include a foreline coupled with the processing chamber, the foreline defining a fluid conduit. The systems may include a radical generator having an inlet and an outlet. The outlet may be fluidly coupled with the foreline. The systems may include a gas source fluidly coupled with the inlet of the radical generator. The systems may include a throttle valve coupled with the foreline downstream of the radical generator.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Khokan Chandra Paul, Truong Van Nguyen, Kelvin Chan, Diwakar Kedlaya, Anantha K. Subramani, Abdul Aziz Khaja, Vijet Patil, Yusheng Fang, Liangfa Hu, Prashant Kumar Kulshreshtha
  • Patent number: 11814716
    Abstract: Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface of the faceplate and the substrate support may at least partially define a processing region within the semiconductor processing chamber. The faceplate may be characterized by a central axis, and the faceplate may define a plurality of apertures through the faceplate. The faceplate may define a central recess about the central axis extending from the second surface of the faceplate to a depth less than a thickness of the faceplate.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: November 14, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Fang Ruan, Prashant Kumar Kulshreshtha, Jiheng Zhao, Diwakar Kedlaya
  • Patent number: 11810764
    Abstract: Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface of the faceplate and the substrate support may at least partially define a processing region within the semiconductor processing chamber. The faceplate may be characterized by a central axis, and the faceplate may define a plurality of apertures through the faceplate. The faceplate may define a plurality of recesses extending about and radially outward of the plurality of apertures.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: November 7, 2023
    Inventors: Fang Ruan, Prashant Kumar Kulshreshtha, Rajaram Narayanan, Diwakar Kedlaya
  • Patent number: 11804363
    Abstract: Exemplary semiconductor processing chambers may include an inlet manifold defining a central aperture. The inlet manifold may also define a first channel and a second channel, and each of the channels may extend through the inlet manifold radially outward of the central aperture. The chambers may also include a gasbox characterized by a first surface facing the inlet manifold and a second surface opposite the first. The gasbox may define a central aperture aligned with the central aperture of the inlet manifold. The gasbox may define a first annular channel in the first surface extending about the central aperture of the gasbox and fluidly coupled with the first channel of the inlet manifold. The gasbox may define a second annular channel extending radially outward of the first and fluidly coupled with the second channel of the inlet manifold. The second annular channel may be fluidly isolated from the first.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: October 31, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Fang Ruan, Diwakar Kedlaya, Truong Van Nguyen, Mingle Tong, Sherry L. Mings, Venkata Sharat Chandra Parimi
  • Patent number: 11798820
    Abstract: A system may include a main line for delivering a first gas, and a sensor for measuring a concentration of a precursor in the first gas delivered through the main line. The system may further include first and second sublines for providing fluid access to first and second processing chambers, respectively. The first subline may include a first flow controller for controlling the first gas flowed through the first subline. The second subline may include a second flow controller for controlling the first gas flowed through the second subline. A delivery controller may be configured to control the first and second flow controllers based on the measured concentration of the precursor to deliver a first mixture of the first gas and a second gas and a second mixture of the first and second gases into the first and second semiconductor processing chambers, respectively.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: October 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Diwakar Kedlaya, Fang Ruan, Zubin Huang, Ganesh Balasubramanian, Kaushik Alayavalli, Martin Seamons, Kwangduk Lee, Rajaram Narayanan, Karthik Janakiraman
  • Publication number: 20230203652
    Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the boron-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the silicon-containing precursor or the boron-containing precursor is greater than or about 1:1. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber.
    Type: Application
    Filed: March 2, 2023
    Publication date: June 29, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Yi Yang, Krishna Nittala, Karthik Janakiraman, Aykut Aydin, Diwakar Kedlaya
  • Patent number: 11682544
    Abstract: Semiconductor processing systems according to embodiments of the present technology may include a chamber body having sidewalls and a base. The chamber body may define an internal volume. The systems may include a substrate support assembly having a shaft and a platen coupled with the shaft along a first surface of the platen. The semiconductor processing systems may include a cover plate positioned on the platen of the substrate support assembly along a second surface of the platen opposite the first surface. The cover plate may include a flange extending about an exterior region of the cover plate. The flange may be in direct contact with the platen. The cover plate may include an upper wall vertically offset from the flange. An interior volume may be defined between the upper wall and the platen of the substrate support assembly.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: June 20, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Venkata Sharat Chandra Parimi, Satish Radhakrishnan, Diwakar Kedlaya, Fang Ruan, Amit Bansal
  • Publication number: 20230146981
    Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon as-deposited may be characterized by less than or about 3% hydrogen incorporation.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 11, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Rui Cheng, Diwakar Kedlaya, Karthik Janakiraman, Gautam K. Hemani, Krishna Nittala, Alicia J. Lustgraaf, Zubin Huang, Brett Spaulding, Shashank Sharma, Kelvin Chan
  • Publication number: 20230118964
    Abstract: A target concentration profile for a film to be deposited on a surface of a substrate during a deposition process for the substrate at a process chamber of a manufacturing system is identified. Data of the target concentration profile is processed using a model. The model outputs a set of deposition process settings that corresponds to the target concentration profile. One or more operations of the deposition process are performed in accordance with the set of deposition process settings.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Anton V. Baryshnikov, Aykut Aydin, Zubin Huang, Rui Cheng, Yi Yang, Diwakar Kedlaya, Venkatanarayana Shankaramurthy, Krishna Nittala, Karthik Janakiraman
  • Patent number: 11618949
    Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the boron-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the silicon-containing precursor or the boron-containing precursor is greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: April 4, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Yi Yang, Krishna Nittala, Karthik Janakiraman, Aykut Aydin, Diwakar Kedlaya
  • Publication number: 20230093450
    Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.
    Type: Application
    Filed: November 30, 2022
    Publication date: March 23, 2023
    Inventors: Tzu-shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KEDLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
  • Publication number: 20230033058
    Abstract: Exemplary semiconductor processing systems may include an inductively coupled plasma source. The systems may include an RF power source that is electrically coupled with the inductively coupled plasma source. The systems may include a first gas source fluidly coupled with the inductively coupled plasma source. The systems may include a second gas source. The systems may include a dual-channel showerhead assembly defining a first plurality of apertures and a second plurality of apertures. The first plurality of apertures may be fluidly coupled with the inductively coupled plasma source. The second plurality of apertures are fluidly coupled with the second gas source.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 2, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Khokan Chandra Paul, Truong Van Nguyen, Diwakar Kedlaya, Maziar Aghvami, Vijet Patil, Shashank Sharma
  • Publication number: 20230023764
    Abstract: Methods and apparatus for surface profiling and texturing of chamber components for use in a process chamber, such surface-profiled or textured chamber components, and method of use of same are provided herein. In some embodiments, a method includes measuring a parameter of a reference substrate or a heated pedestal using one or more sensors and modifying a surface of a chamber component physically based on the measured parameter.
    Type: Application
    Filed: December 15, 2020
    Publication date: January 26, 2023
    Inventors: David W. GROECHEL, Michael R. RICE, Gang Grant PENG, Rui CHENG, Zubin HUANG, Han WANG, Karthik JANAKIRAMAN, Diwakar KEDLAYA, Paul L. BRILLHART, Abdul Aziz KHAJA
  • Patent number: 11562902
    Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by less than or about 3% hydrogen incorporation.
    Type: Grant
    Filed: July 19, 2020
    Date of Patent: January 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Rui Cheng, Diwakar Kedlaya, Karthik Janakiraman, Gautam K. Hemani, Krishna Nittala, Alicia J. Lustgraaf, Zubin Huang, Brett Spaulding, Shashank Sharma, Kelvin Chan
  • Patent number: 11532525
    Abstract: Methods and systems for controlling concentration profiles of deposited films using machine learning are provided. Data associated with a target concentration profile for a film to be deposited on a surface of a substrate during a deposition process for the substrate is provided as input to a trained machine learning model. One or more outputs of the trained machine learning model are obtained. Process recipe data identifying one or more sets of deposition process settings is determined from the one or more outputs. For each set of deposition process setting, an indication of a level of confidence that a respective set of deposition process settings corresponds to the target concentration profile for the film to be deposited on the substrate is also determined.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: December 20, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Anton V Baryshnikov, Aykut Aydin, Zubin Huang, Rui Cheng, Yi Yang, Diwakar Kedlaya, Venkatanarayana Shankaramurthy, Krishna Nittala, Karthik Janakiraman