Patents by Inventor Diwakar SINGH

Diwakar SINGH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS
    Publication number: 20230290387
    Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Inventors: Pradeep RAJ, Rahul SAHU, Sharad Kumar GUPTA, Hemant PATEL, Diwakar SINGH
  • Memory
    Patent number: 11424250
    Abstract: An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: August 23, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kalyan Kumar Oruganti, Sreeram Gurram, Venkata Balakrishna Reddy Thumu, Pradeep Jayadev Kodlipet, Diwakar Singh, Channappa Desai, Sunil Sharma, Anne Srikanth, Yandong Gao
  • MEMORY
    Publication number: 20220068940
    Abstract: An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 3, 2022
    Inventors: Kalyan Kumar ORUGANTI, Sreeram GURRAM, Venkata Balakrishna Reddy THUMU, Pradeep Jayadev KODLIPET, Diwakar SINGH, Channappa DESAI, Sunil SHARMA, Anne SRIKANTH, Yandong GAO